Mercurial > ~darius > hgwebdir.cgi > stm32temp
annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt @ 89:fc21fb5b171b default tip
Make error message more useful
author | Daniel O'Connor <darius@dons.net.au> |
---|---|
date | Fri, 13 Mar 2015 11:39:59 +1030 |
parents | c59513fd84fb |
children |
rev | line source |
---|---|
0
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
2 @page TIM_Cascade_Synchro TIM Cascade Synchro example |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
3 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
4 @verbatim |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
5 ******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
6 * @file TIM/Cascade_Synchro/readme.txt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
7 * @author MCD Application Team |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
8 * @version V3.5.0 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
9 * @date 08-April-2011 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
10 * @brief Description of the TIM Cascade Synchro example. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
11 ****************************************************************************** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
18 ****************************************************************************** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
19 @endverbatim |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
20 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
21 @par Example Description |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
22 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
23 This example shows how to synchronize TIM peripherals in cascade mode. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
24 In this example three timers are used: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
25 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
26 Timers synchronisation in cascade mode: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
27 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
28 1/TIM2 is configured as Master Timer: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
29 - PWM Mode is used |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
30 - The TIM2 Update event is used as Trigger Output |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
31 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
32 2/TIM3 is slave for TIM2 and Master for TIM4, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
33 - PWM Mode is used |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
34 - The ITR1(TIM2) is used as input trigger |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
35 - Gated mode is used, so start and stop of slave counter |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
36 are controlled by the Master trigger output signal(TIM2 update event). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
37 - The TIM3 Update event is used as Trigger Output. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
38 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
39 3/TIM4 is slave for TIM3, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
40 - PWM Mode is used |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
41 - The ITR2(TIM3) is used as input trigger |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
42 - Gated mode is used, so start and stop of slave counter are controlled by the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
43 Master trigger output signal(TIM3 update event). |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
44 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
45 o For Low-density, Medium-density, High-density and Connectivity line devices: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
46 The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
47 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
48 The Master Timer TIM2 is running at TIM2 frequency : |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
49 TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
50 and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
51 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
52 The TIM3 is running at: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
53 (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle equal |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
54 to TIM3_CCR1/(TIM3_ARR + 1) = 25% |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
55 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
56 The TIM4 is running at: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
57 (TIM3 frequency)/ (TIM4 period + 1) = 17.578 Hz and a duty cycle equal |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
58 to TIM4_CCR1/(TIM4_ARR + 1) = 25% |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
59 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
60 o For Low-Density Value line, Medium-Density and High-Density Value line devices: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
61 The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
62 So TIM2 frequency = 93.750 KHz, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
63 TIM3 is running at 23.437 KHz, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
64 and TIM4 is running at 5.85 KHz |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
65 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
66 @par Directory contents |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
67 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
68 - TIM/Cascade_Synchro/stm32f10x_conf.h Library Configuration file |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
69 - TIM/Cascade_Synchro/stm32f10x_it.c Interrupt handlers |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
70 - TIM/Cascade_Synchro/stm32f10x_it.h Interrupt handlers header file |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
71 - TIM/Cascade_Synchro/main.c Main program |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
72 - TIM/Cascade_Synchro/system_stm32f10x.c STM32F10x system source file |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
73 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
74 @par Hardware and Software environment |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
75 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
76 - This example runs on STM32F10x Connectivity line, High-Density, High-Density |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
77 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
78 and Low-Density Value line Devices. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
79 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
80 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
81 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
82 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
83 evaluation boards and can be easily tailored to any other supported device |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
84 and development board. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
85 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
86 - STM3210C-EVAL Set-up |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
87 - Connect the following pins to an oscilloscope to monitor the different |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
88 waveforms: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
89 - TIM2 CH1 (PA.00) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
90 - TIM3 CH1 (PC.06) Remapped pin |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
91 - TIM4 CH1 (PB.06) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
92 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
93 - STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
94 - Connect the following pins to an oscilloscope to monitor the different |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
95 waveforms: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
96 - TIM2 CH1 (PA.00) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
97 - TIM3 CH1 (PA.06) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
98 - TIM4 CH1 (PB.06) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
99 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
100 @par How to use it ? |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
101 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
102 In order to make the program work, you must do the following : |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
103 - Copy all source files from this example folder to the template folder under |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
104 Project\STM32F10x_StdPeriph_Template |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
105 - Open your preferred toolchain |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
106 - Rebuild all files and load your image into target memory |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
107 - Run the example |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
108 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
109 @note |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
110 - Low-density Value line devices are STM32F100xx microcontrollers where the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
111 Flash memory density ranges between 16 and 32 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
112 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
113 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
114 - Medium-density Value line devices are STM32F100xx microcontrollers where |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
115 the Flash memory density ranges between 64 and 128 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
116 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
117 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
118 - High-density Value line devices are STM32F100xx microcontrollers where |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
119 the Flash memory density ranges between 256 and 512 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
120 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
121 the Flash memory density ranges between 256 and 512 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
122 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
123 the Flash memory density ranges between 512 and 1024 Kbytes. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
124 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
125 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
126 * <h3><center>© COPYRIGHT 2011 STMicroelectronics</center></h3> |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
127 */ |