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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md_vl.s @ 89:fc21fb5b171b default tip

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Make error message more useful
author Daniel O'Connor <darius@dons.net.au>
date Fri, 13 Mar 2015 11:39:59 +1030
parents c59513fd84fb
children
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c59513fd84fb Initial commit of STM32 test code.
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1 /**
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2 ******************************************************************************
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3 * @file startup_stm32f10x_md_vl.s
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4 * @author MCD Application Team
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5 * @version V3.5.0
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6 * @date 11-March-2011
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7 * @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7
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8 * toolchain.
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9 * This module performs:
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10 * - Set the initial SP
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11 * - Set the initial PC == Reset_Handler,
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12 * - Set the vector table entries with the exceptions ISR address
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13 * - Configure the clock system
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14 * - Branches to main in the C library (which eventually
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15 * calls main()).
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16 * After Reset the Cortex-M3 processor is in Thread mode,
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17 * priority is Privileged, and the Stack is set to Main.
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18 ******************************************************************************
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19 * @attention
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20 *
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21 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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22 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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23 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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24 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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25 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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26 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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27 *
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28 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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29 ******************************************************************************
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30 */
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31
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32 .syntax unified
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33 .cpu cortex-m3
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34 .fpu softvfp
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35 .thumb
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36
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37 .global g_pfnVectors
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38 .global Default_Handler
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39
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40 /* start address for the initialization values of the .data section.
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41 defined in linker script */
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42 .word _sidata
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43 /* start address for the .data section. defined in linker script */
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44 .word _sdata
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45 /* end address for the .data section. defined in linker script */
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46 .word _edata
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47 /* start address for the .bss section. defined in linker script */
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48 .word _sbss
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49 /* end address for the .bss section. defined in linker script */
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50 .word _ebss
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51
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52 .equ BootRAM, 0xF108F85F
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53 /**
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54 * @brief This is the code that gets called when the processor first
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55 * starts execution following a reset event. Only the absolutely
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56 * necessary set is performed, after which the application
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57 * supplied main() routine is called.
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58 * @param None
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59 * @retval None
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60 */
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61
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62 .section .text.Reset_Handler
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63 .weak Reset_Handler
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64 .type Reset_Handler, %function
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65 Reset_Handler:
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66
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67 /* Copy the data segment initializers from flash to SRAM */
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68 movs r1, #0
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69 b LoopCopyDataInit
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70
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71 CopyDataInit:
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72 ldr r3, =_sidata
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73 ldr r3, [r3, r1]
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74 str r3, [r0, r1]
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75 adds r1, r1, #4
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76
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77 LoopCopyDataInit:
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78 ldr r0, =_sdata
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79 ldr r3, =_edata
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80 adds r2, r0, r1
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81 cmp r2, r3
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82 bcc CopyDataInit
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83 ldr r2, =_sbss
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84 b LoopFillZerobss
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85 /* Zero fill the bss segment. */
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86 FillZerobss:
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87 movs r3, #0
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88 str r3, [r2], #4
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89
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90 LoopFillZerobss:
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91 ldr r3, = _ebss
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92 cmp r2, r3
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93 bcc FillZerobss
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94 /* Call the clock system intitialization function.*/
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95 bl SystemInit
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96 /* Call the application's entry point.*/
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97 bl main
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98 bx lr
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99 .size Reset_Handler, .-Reset_Handler
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100
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101 /**
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102 * @brief This is the code that gets called when the processor receives an
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103 * unexpected interrupt. This simply enters an infinite loop, preserving
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104 * the system state for examination by a debugger.
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105 * @param None
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106 * @retval None
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107 */
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108 .section .text.Default_Handler,"ax",%progbits
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109 Default_Handler:
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110 Infinite_Loop:
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111 b Infinite_Loop
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112 .size Default_Handler, .-Default_Handler
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113 /******************************************************************************
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114 *
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115 * The minimal vector table for a Cortex M3. Note that the proper constructs
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116 * must be placed on this to ensure that it ends up at physical address
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117 * 0x0000.0000.
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118 *
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119 ******************************************************************************/
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120 .section .isr_vector,"a",%progbits
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121 .type g_pfnVectors, %object
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122 .size g_pfnVectors, .-g_pfnVectors
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123
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124 g_pfnVectors:
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125 .word _estack
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126 .word Reset_Handler
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127 .word NMI_Handler
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128 .word HardFault_Handler
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129 .word MemManage_Handler
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130 .word BusFault_Handler
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131 .word UsageFault_Handler
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132 .word 0
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133 .word 0
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134 .word 0
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135 .word 0
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136 .word SVC_Handler
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137 .word DebugMon_Handler
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138 .word 0
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139 .word PendSV_Handler
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140 .word SysTick_Handler
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141 .word WWDG_IRQHandler
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142 .word PVD_IRQHandler
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143 .word TAMPER_IRQHandler
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144 .word RTC_IRQHandler
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145 .word FLASH_IRQHandler
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146 .word RCC_IRQHandler
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147 .word EXTI0_IRQHandler
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148 .word EXTI1_IRQHandler
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149 .word EXTI2_IRQHandler
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150 .word EXTI3_IRQHandler
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151 .word EXTI4_IRQHandler
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152 .word DMA1_Channel1_IRQHandler
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Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
153 .word DMA1_Channel2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
154 .word DMA1_Channel3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
155 .word DMA1_Channel4_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
156 .word DMA1_Channel5_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
157 .word DMA1_Channel6_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
158 .word DMA1_Channel7_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
159 .word ADC1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
160 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
161 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
162 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
163 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
164 .word EXTI9_5_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
165 .word TIM1_BRK_TIM15_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
166 .word TIM1_UP_TIM16_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
167 .word TIM1_TRG_COM_TIM17_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
168 .word TIM1_CC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
169 .word TIM2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
170 .word TIM3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
171 .word TIM4_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
172 .word I2C1_EV_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
173 .word I2C1_ER_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
174 .word I2C2_EV_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
175 .word I2C2_ER_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
176 .word SPI1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
177 .word SPI2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
178 .word USART1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
179 .word USART2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
180 .word USART3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
181 .word EXTI15_10_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
182 .word RTCAlarm_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
183 .word CEC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
184 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
185 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
186 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
187 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
188 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
189 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
190 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
191 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
192 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
193 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
194 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
195 .word TIM6_DAC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
196 .word TIM7_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
197 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
198 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
199 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
200 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
201 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
202 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
203 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
204 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
205 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
206 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
207 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
208 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
209 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
210 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
211 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
212 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
213 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
214 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
215 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
216 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
217 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
218 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
219 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
220 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
221 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
222 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
223 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
224 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
225 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
226 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
227 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
228 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
229 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
230 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
231 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
232 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
233 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
234 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
235 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
236 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
237 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
238 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
239 .word 0
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
240 .word BootRAM /* @0x01CC. This is for boot in RAM mode for
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
241 STM32F10x Medium Value Line Density devices. */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
242
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
243 /*******************************************************************************
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
244 * Provide weak aliases for each Exception handler to the Default_Handler.
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
245 * As they are weak aliases, any function with the same name will override
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
246 * this definition.
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
247 *******************************************************************************/
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
248
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
249 .weak NMI_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
250 .thumb_set NMI_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
251
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
252 .weak HardFault_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
253 .thumb_set HardFault_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
254
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
255 .weak MemManage_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
256 .thumb_set MemManage_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
257
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
258 .weak BusFault_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
259 .thumb_set BusFault_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
260
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
261 .weak UsageFault_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
262 .thumb_set UsageFault_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
263
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
264 .weak SVC_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
265 .thumb_set SVC_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
266
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
267 .weak DebugMon_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
268 .thumb_set DebugMon_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
269
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
270 .weak PendSV_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
271 .thumb_set PendSV_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
272
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
273 .weak SysTick_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
274 .thumb_set SysTick_Handler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
275
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
276 .weak WWDG_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
277 .thumb_set WWDG_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
278
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
279 .weak PVD_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
280 .thumb_set PVD_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
281
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
282 .weak TAMPER_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
283 .thumb_set TAMPER_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
284
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
285 .weak RTC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
286 .thumb_set RTC_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
287
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
288 .weak FLASH_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
289 .thumb_set FLASH_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
290
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
291 .weak RCC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
292 .thumb_set RCC_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
293
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
294 .weak EXTI0_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
295 .thumb_set EXTI0_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
296
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
297 .weak EXTI1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
298 .thumb_set EXTI1_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
299
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
300 .weak EXTI2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
301 .thumb_set EXTI2_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
302
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
303 .weak EXTI3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
304 .thumb_set EXTI3_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
305
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
306 .weak EXTI4_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
307 .thumb_set EXTI4_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
308
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
309 .weak DMA1_Channel1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
310 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
311
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
312 .weak DMA1_Channel2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
313 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
314
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
315 .weak DMA1_Channel3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
316 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
317
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
318 .weak DMA1_Channel4_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
319 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
320
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
321 .weak DMA1_Channel5_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
322 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
323
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
324 .weak DMA1_Channel6_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
325 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
326
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
327 .weak DMA1_Channel7_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
328 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
329
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
330 .weak ADC1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
331 .thumb_set ADC1_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
332
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
333 .weak EXTI9_5_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
334 .thumb_set EXTI9_5_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
335
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
336 .weak TIM1_BRK_TIM15_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
337 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
338
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
339 .weak TIM1_UP_TIM16_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
340 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
341
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
342 .weak TIM1_TRG_COM_TIM17_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
343 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
344
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
345 .weak TIM1_CC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
346 .thumb_set TIM1_CC_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
347
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
348 .weak TIM2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
349 .thumb_set TIM2_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
350
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
351 .weak TIM3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
352 .thumb_set TIM3_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
353
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
354 .weak TIM4_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
355 .thumb_set TIM4_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
356
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
357 .weak I2C1_EV_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
358 .thumb_set I2C1_EV_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
359
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
360 .weak I2C1_ER_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
361 .thumb_set I2C1_ER_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
362
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
363 .weak I2C2_EV_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
364 .thumb_set I2C2_EV_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
365
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
366 .weak I2C2_ER_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
367 .thumb_set I2C2_ER_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
368
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
369 .weak SPI1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
370 .thumb_set SPI1_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
371
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
372 .weak SPI2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
373 .thumb_set SPI2_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
374
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
375 .weak USART1_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
376 .thumb_set USART1_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
377
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
378 .weak USART2_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
379 .thumb_set USART2_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
380
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
381 .weak USART3_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
382 .thumb_set USART3_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
383
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
384 .weak EXTI15_10_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
385 .thumb_set EXTI15_10_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
386
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
387 .weak RTCAlarm_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
388 .thumb_set RTCAlarm_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
389
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
390 .weak CEC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
391 .thumb_set CEC_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
392
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
393 .weak TIM6_DAC_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
394 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
395
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
396 .weak TIM7_IRQHandler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
397 .thumb_set TIM7_IRQHandler,Default_Handler
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
398
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
399 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/