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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h @ 0:c59513fd84fb
Initial commit of STM32 test code.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Mon, 03 Oct 2011 21:19:15 +1030 |
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1 /**************************************************************************//** |
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2 * @file core_cm3.h |
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3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
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4 * @version V1.30 |
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5 * @date 30. October 2009 |
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6 * |
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7 * @note |
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8 * Copyright (C) 2009 ARM Limited. All rights reserved. |
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9 * |
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10 * @par |
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M |
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12 * processor based microcontrollers. This file can be freely distributed |
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13 * within development tools that are supporting such ARM based processors. |
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14 * |
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15 * @par |
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
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21 * |
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22 ******************************************************************************/ |
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23 |
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24 #ifndef __CM3_CORE_H__ |
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25 #define __CM3_CORE_H__ |
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26 |
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27 /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration |
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28 * |
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29 * List of Lint messages which will be suppressed and not shown: |
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30 * - Error 10: \n |
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31 * register uint32_t __regBasePri __asm("basepri"); \n |
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32 * Error 10: Expecting ';' |
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33 * . |
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34 * - Error 530: \n |
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35 * return(__regBasePri); \n |
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36 * Warning 530: Symbol '__regBasePri' (line 264) not initialized |
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37 * . |
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38 * - Error 550: \n |
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39 * __regBasePri = (basePri & 0x1ff); \n |
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40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed |
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41 * . |
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42 * - Error 754: \n |
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43 * uint32_t RESERVED0[24]; \n |
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44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced |
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45 * . |
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46 * - Error 750: \n |
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47 * #define __CM3_CORE_H__ \n |
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48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced |
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49 * . |
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50 * - Error 528: \n |
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51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n |
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52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced |
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53 * . |
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54 * - Error 751: \n |
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55 * } InterruptType_Type; \n |
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56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced |
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57 * . |
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58 * Note: To re-enable a Message, insert a space before 'lint' * |
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59 * |
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60 */ |
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61 |
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62 /*lint -save */ |
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63 /*lint -e10 */ |
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64 /*lint -e530 */ |
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65 /*lint -e550 */ |
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66 /*lint -e754 */ |
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67 /*lint -e750 */ |
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68 /*lint -e528 */ |
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69 /*lint -e751 */ |
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70 |
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71 |
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72 /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions |
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73 This file defines all structures and symbols for CMSIS core: |
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74 - CMSIS version number |
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75 - Cortex-M core registers and bitfields |
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76 - Cortex-M core peripheral base address |
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77 @{ |
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78 */ |
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79 |
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80 #ifdef __cplusplus |
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81 extern "C" { |
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82 #endif |
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83 |
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84 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ |
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85 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ |
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86 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
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87 |
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88 #define __CORTEX_M (0x03) /*!< Cortex core */ |
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89 |
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90 #include <stdint.h> /* Include standard types */ |
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91 |
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92 #if defined (__ICCARM__) |
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93 #include <intrinsics.h> /* IAR Intrinsics */ |
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94 #endif |
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95 |
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96 |
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97 #ifndef __NVIC_PRIO_BITS |
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98 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ |
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99 #endif |
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100 |
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101 |
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102 |
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103 |
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104 /** |
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105 * IO definitions |
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106 * |
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107 * define access restrictions to peripheral registers |
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108 */ |
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109 |
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110 #ifdef __cplusplus |
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111 #define __I volatile /*!< defines 'read only' permissions */ |
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112 #else |
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113 #define __I volatile const /*!< defines 'read only' permissions */ |
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114 #endif |
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115 #define __O volatile /*!< defines 'write only' permissions */ |
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116 #define __IO volatile /*!< defines 'read / write' permissions */ |
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117 |
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118 |
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119 |
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120 /******************************************************************************* |
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121 * Register Abstraction |
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122 ******************************************************************************/ |
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123 /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register |
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124 @{ |
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125 */ |
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126 |
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127 |
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128 /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC |
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129 memory mapped structure for Nested Vectored Interrupt Controller (NVIC) |
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130 @{ |
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131 */ |
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132 typedef struct |
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133 { |
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134 __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ |
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135 uint32_t RESERVED0[24]; |
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136 __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ |
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137 uint32_t RSERVED1[24]; |
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138 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ |
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139 uint32_t RESERVED2[24]; |
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140 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ |
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141 uint32_t RESERVED3[24]; |
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142 __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ |
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143 uint32_t RESERVED4[56]; |
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144 __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ |
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145 uint32_t RESERVED5[644]; |
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146 __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ |
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147 } NVIC_Type; |
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148 /*@}*/ /* end of group CMSIS_CM3_NVIC */ |
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149 |
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150 |
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151 /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB |
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152 memory mapped structure for System Control Block (SCB) |
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153 @{ |
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154 */ |
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155 typedef struct |
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156 { |
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157 __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ |
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158 __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ |
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159 __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ |
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160 __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ |
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161 __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ |
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162 __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ |
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163 __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
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164 __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ |
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165 __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ |
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166 __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ |
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167 __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ |
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168 __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ |
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169 __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ |
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170 __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ |
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171 __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ |
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172 __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ |
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173 __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ |
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174 __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ |
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175 __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ |
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176 } SCB_Type; |
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177 |
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178 /* SCB CPUID Register Definitions */ |
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179 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
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180 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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181 |
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182 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
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183 #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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184 |
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185 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
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186 #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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187 |
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188 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
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189 #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
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190 |
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191 /* SCB Interrupt Control State Register Definitions */ |
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192 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
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193 #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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194 |
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195 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
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196 #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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197 |
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198 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
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199 #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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200 |
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201 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
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202 #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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203 |
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204 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
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205 #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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206 |
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207 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
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208 #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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209 |
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210 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
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211 #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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212 |
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213 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
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214 #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
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215 |
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216 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
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217 #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
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218 |
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219 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
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220 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
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221 |
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222 /* SCB Interrupt Control State Register Definitions */ |
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223 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
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224 #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
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225 |
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226 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
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227 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
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228 |
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229 /* SCB Application Interrupt and Reset Control Register Definitions */ |
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230 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
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231 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
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232 |
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233 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
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234 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
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235 |
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236 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
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237 #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
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238 |
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239 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
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240 #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
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241 |
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242 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
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243 #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
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244 |
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245 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
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246 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
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247 |
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248 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
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249 #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ |
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250 |
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251 /* SCB System Control Register Definitions */ |
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252 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
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253 #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
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254 |
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255 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
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256 #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
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257 |
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258 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
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259 #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
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260 |
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261 /* SCB Configuration Control Register Definitions */ |
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262 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
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263 #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
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264 |
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265 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
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266 #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
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267 |
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268 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
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269 #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
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270 |
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271 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
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272 #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
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273 |
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274 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
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275 #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
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276 |
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277 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
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278 #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ |
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279 |
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280 /* SCB System Handler Control and State Register Definitions */ |
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281 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
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282 #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
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283 |
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284 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
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285 #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
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286 |
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287 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
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288 #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
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289 |
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290 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
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291 #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
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292 |
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293 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
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294 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
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295 |
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296 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
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297 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
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298 |
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299 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
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300 #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
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301 |
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302 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
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303 #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
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304 |
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305 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
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306 #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
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307 |
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308 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
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309 #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
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310 |
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311 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
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312 #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
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313 |
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314 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
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315 #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
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316 |
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317 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
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318 #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
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319 |
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320 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
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321 #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
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322 |
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323 /* SCB Configurable Fault Status Registers Definitions */ |
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324 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
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325 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
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326 |
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327 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
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328 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
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329 |
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330 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
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331 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
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332 |
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333 /* SCB Hard Fault Status Registers Definitions */ |
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334 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
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335 #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
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336 |
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337 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
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338 #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
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339 |
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340 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
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341 #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
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342 |
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343 /* SCB Debug Fault Status Register Definitions */ |
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344 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
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345 #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
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346 |
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347 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
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348 #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
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349 |
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350 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
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351 #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
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352 |
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353 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
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354 #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
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355 |
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356 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
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357 #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ |
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358 /*@}*/ /* end of group CMSIS_CM3_SCB */ |
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359 |
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360 |
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361 /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick |
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362 memory mapped structure for SysTick |
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363 @{ |
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364 */ |
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365 typedef struct |
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366 { |
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367 __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ |
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368 __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ |
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369 __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ |
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370 __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ |
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371 } SysTick_Type; |
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372 |
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373 /* SysTick Control / Status Register Definitions */ |
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374 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
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375 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
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376 |
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377 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
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378 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
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379 |
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380 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
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381 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
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382 |
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383 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
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384 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
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385 |
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386 /* SysTick Reload Register Definitions */ |
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387 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
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388 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
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389 |
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390 /* SysTick Current Register Definitions */ |
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391 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
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392 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
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393 |
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394 /* SysTick Calibration Register Definitions */ |
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395 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
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396 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
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397 |
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398 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
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399 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
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400 |
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401 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
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402 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
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403 /*@}*/ /* end of group CMSIS_CM3_SysTick */ |
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404 |
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405 |
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406 /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM |
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407 memory mapped structure for Instrumentation Trace Macrocell (ITM) |
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408 @{ |
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409 */ |
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410 typedef struct |
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411 { |
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412 __O union |
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413 { |
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414 __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ |
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415 __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ |
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416 __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ |
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417 } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ |
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418 uint32_t RESERVED0[864]; |
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419 __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ |
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420 uint32_t RESERVED1[15]; |
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421 __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ |
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422 uint32_t RESERVED2[15]; |
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423 __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ |
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424 uint32_t RESERVED3[29]; |
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425 __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ |
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426 __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ |
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427 __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ |
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428 uint32_t RESERVED4[43]; |
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429 __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ |
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430 __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ |
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431 uint32_t RESERVED5[6]; |
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432 __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ |
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433 __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ |
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434 __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ |
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435 __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ |
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436 __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ |
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437 __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ |
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438 __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ |
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439 __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ |
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440 __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ |
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441 __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ |
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442 __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ |
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443 __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ |
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444 } ITM_Type; |
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445 |
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446 /* ITM Trace Privilege Register Definitions */ |
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447 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
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448 #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ |
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449 |
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450 /* ITM Trace Control Register Definitions */ |
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451 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
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452 #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
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453 |
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454 #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ |
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455 #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ |
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456 |
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457 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
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458 #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
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459 |
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460 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
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461 #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
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462 |
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463 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
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464 #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
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465 |
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466 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
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467 #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
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468 |
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469 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
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470 #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
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471 |
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472 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
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473 #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ |
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474 |
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475 /* ITM Integration Write Register Definitions */ |
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476 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
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477 #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ |
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478 |
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479 /* ITM Integration Read Register Definitions */ |
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480 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
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481 #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ |
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482 |
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483 /* ITM Integration Mode Control Register Definitions */ |
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484 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
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485 #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ |
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486 |
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487 /* ITM Lock Status Register Definitions */ |
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488 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
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489 #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
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490 |
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491 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
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492 #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
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493 |
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494 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
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495 #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ |
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496 /*@}*/ /* end of group CMSIS_CM3_ITM */ |
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497 |
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498 |
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499 /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type |
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500 memory mapped structure for Interrupt Type |
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501 @{ |
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502 */ |
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503 typedef struct |
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504 { |
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505 uint32_t RESERVED0; |
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506 __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ |
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507 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) |
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508 __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ |
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509 #else |
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510 uint32_t RESERVED1; |
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511 #endif |
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512 } InterruptType_Type; |
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513 |
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514 /* Interrupt Controller Type Register Definitions */ |
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515 #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ |
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516 #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ |
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517 |
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518 /* Auxiliary Control Register Definitions */ |
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519 #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ |
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520 #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ |
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521 |
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522 #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ |
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523 #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ |
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524 |
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525 #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ |
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526 #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ |
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527 /*@}*/ /* end of group CMSIS_CM3_InterruptType */ |
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528 |
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529 |
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530 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
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531 /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU |
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532 memory mapped structure for Memory Protection Unit (MPU) |
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533 @{ |
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534 */ |
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535 typedef struct |
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536 { |
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537 __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ |
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538 __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ |
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539 __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ |
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540 __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ |
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541 __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ |
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542 __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ |
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543 __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ |
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544 __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ |
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545 __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ |
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546 __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ |
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547 __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ |
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548 } MPU_Type; |
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549 |
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550 /* MPU Type Register */ |
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551 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
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552 #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
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553 |
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554 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
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555 #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
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556 |
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557 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
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558 #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
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559 |
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560 /* MPU Control Register */ |
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561 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
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562 #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
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563 |
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564 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
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565 #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
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566 |
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567 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
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568 #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
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569 |
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570 /* MPU Region Number Register */ |
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571 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
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572 #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
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|
573 |
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574 /* MPU Region Base Address Register */ |
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575 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
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576 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
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577 |
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578 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
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579 #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
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580 |
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581 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
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582 #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
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583 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
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584 /* MPU Region Attribute and Size Register */ |
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585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ |
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586 #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ |
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587 |
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588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ |
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589 #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ |
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590 |
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parents:
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591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ |
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592 #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ |
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593 |
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594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ |
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595 #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ |
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596 |
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597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ |
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598 #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ |
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599 |
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600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ |
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601 #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ |
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602 |
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Initial commit of STM32 test code.
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603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
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604 #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
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605 |
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606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
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607 #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
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608 |
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609 #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
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610 #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
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611 |
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612 /*@}*/ /* end of group CMSIS_CM3_MPU */ |
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613 #endif |
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614 |
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615 |
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616 /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug |
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617 memory mapped structure for Core Debug Register |
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618 @{ |
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619 */ |
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620 typedef struct |
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621 { |
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622 __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ |
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623 __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ |
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624 __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ |
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625 __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ |
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626 } CoreDebug_Type; |
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627 |
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628 /* Debug Halting Control and Status Register */ |
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629 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
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630 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
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631 |
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632 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
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633 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
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634 |
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635 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
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636 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
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637 |
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638 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
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639 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
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640 |
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641 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
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642 #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
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643 |
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644 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
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645 #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
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646 |
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647 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
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648 #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
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649 |
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650 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
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651 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
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652 |
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653 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
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654 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
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655 |
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656 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
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657 #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
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658 |
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659 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
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660 #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
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661 |
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662 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
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663 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
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664 |
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665 /* Debug Core Register Selector Register */ |
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666 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
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667 #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
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668 |
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669 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
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670 #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ |
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671 |
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672 /* Debug Exception and Monitor Control Register */ |
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673 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
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674 #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
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675 |
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676 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
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677 #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
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678 |
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679 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
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680 #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
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681 |
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682 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
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683 #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
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684 |
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685 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
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686 #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
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687 |
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688 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
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689 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
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diff
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|
690 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
691 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
692 #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
693 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
694 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
695 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
696 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
697 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
698 #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
699 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
700 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
701 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
702 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
703 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
704 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
705 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
706 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
707 #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
708 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
709 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
710 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
711 /*@}*/ /* end of group CMSIS_CM3_CoreDebug */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
712 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
713 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
714 /* Memory mapping of Cortex-M3 Hardware */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
715 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
716 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
717 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
718 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
719 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
720 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
721 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
722 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
723 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
724 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
725 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
726 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
727 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
728 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
729 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
730 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
731 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
732 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
733 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
734 /*@}*/ /* end of group CMSIS_CM3_core_register */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
735 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
736 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
737 /******************************************************************************* |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
738 * Hardware Abstraction Layer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
739 ******************************************************************************/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
740 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
741 #if defined ( __CC_ARM ) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
742 #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
743 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
744 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
745 #elif defined ( __ICCARM__ ) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
746 #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
747 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
748 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
749 #elif defined ( __GNUC__ ) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
750 #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
751 #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
752 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
753 #elif defined ( __TASKING__ ) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
754 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
755 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
756 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
757 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
758 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
759 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
760 /* ################### Compiler specific Intrinsics ########################### */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
761 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
762 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
763 /* ARM armcc specific functions */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
764 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
765 #define __enable_fault_irq __enable_fiq |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
766 #define __disable_fault_irq __disable_fiq |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
767 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
768 #define __NOP __nop |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
769 #define __WFI __wfi |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
770 #define __WFE __wfe |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
771 #define __SEV __sev |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
772 #define __ISB() __isb(0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
773 #define __DSB() __dsb(0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
774 #define __DMB() __dmb(0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
775 #define __REV __rev |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
776 #define __RBIT __rbit |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
777 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
778 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
779 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
780 #define __STREXB(value, ptr) __strex(value, ptr) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
781 #define __STREXH(value, ptr) __strex(value, ptr) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
782 #define __STREXW(value, ptr) __strex(value, ptr) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
783 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
784 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
785 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
786 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
787 /* intrinsic void __enable_irq(); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
788 /* intrinsic void __disable_irq(); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
789 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
790 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
791 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
792 * @brief Return the Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
793 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
794 * @return ProcessStackPointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
795 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
796 * Return the actual process stack pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
797 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
798 extern uint32_t __get_PSP(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
799 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
800 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
801 * @brief Set the Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
802 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
803 * @param topOfProcStack Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
804 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
805 * Assign the value ProcessStackPointer to the MSP |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
806 * (process stack pointer) Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
807 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
808 extern void __set_PSP(uint32_t topOfProcStack); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
809 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
810 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
811 * @brief Return the Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
812 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
813 * @return Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
814 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
815 * Return the current value of the MSP (main stack pointer) |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
816 * Cortex processor register |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
817 */ |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
818 extern uint32_t __get_MSP(void); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
819 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
820 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
821 * @brief Set the Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
822 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
823 * @param topOfMainStack Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
824 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
825 * Assign the value mainStackPointer to the MSP |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
826 * (main stack pointer) Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
827 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
828 extern void __set_MSP(uint32_t topOfMainStack); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
829 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
830 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
831 * @brief Reverse byte order in unsigned short value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
832 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
833 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
834 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
835 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
836 * Reverse byte order in unsigned short value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
837 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
838 extern uint32_t __REV16(uint16_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
839 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
840 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
841 * @brief Reverse byte order in signed short value with sign extension to integer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
842 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
843 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
844 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
845 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
846 * Reverse byte order in signed short value with sign extension to integer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
847 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
848 extern int32_t __REVSH(int16_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
849 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
850 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
851 #if (__ARMCC_VERSION < 400000) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
852 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
853 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
854 * @brief Remove the exclusive lock created by ldrex |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
855 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
856 * Removes the exclusive lock which is created by ldrex. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
857 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
858 extern void __CLREX(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
859 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
860 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
861 * @brief Return the Base Priority value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
862 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
863 * @return BasePriority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
864 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
865 * Return the content of the base priority register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
866 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
867 extern uint32_t __get_BASEPRI(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
868 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
869 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
870 * @brief Set the Base Priority value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
871 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
872 * @param basePri BasePriority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
873 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
874 * Set the base priority register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
875 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
876 extern void __set_BASEPRI(uint32_t basePri); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
877 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
878 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
879 * @brief Return the Priority Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
880 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
881 * @return PriMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
882 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
883 * Return state of the priority mask bit from the priority mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
884 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
885 extern uint32_t __get_PRIMASK(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
886 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
887 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
888 * @brief Set the Priority Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
889 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
890 * @param priMask PriMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
891 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
892 * Set the priority mask bit in the priority mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
893 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
894 extern void __set_PRIMASK(uint32_t priMask); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
895 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
896 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
897 * @brief Return the Fault Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
898 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
899 * @return FaultMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
900 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
901 * Return the content of the fault mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
902 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
903 extern uint32_t __get_FAULTMASK(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
904 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
905 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
906 * @brief Set the Fault Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
907 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
908 * @param faultMask faultMask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
909 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
910 * Set the fault mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
911 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
912 extern void __set_FAULTMASK(uint32_t faultMask); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
913 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
914 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
915 * @brief Return the Control Register value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
916 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
917 * @return Control value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
918 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
919 * Return the content of the control register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
920 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
921 extern uint32_t __get_CONTROL(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
922 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
923 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
924 * @brief Set the Control Register value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
925 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
926 * @param control Control value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
927 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
928 * Set the control register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
929 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
930 extern void __set_CONTROL(uint32_t control); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
931 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
932 #else /* (__ARMCC_VERSION >= 400000) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
933 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
934 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
935 * @brief Remove the exclusive lock created by ldrex |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
936 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
937 * Removes the exclusive lock which is created by ldrex. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
938 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
939 #define __CLREX __clrex |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
940 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
941 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
942 * @brief Return the Base Priority value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
943 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
944 * @return BasePriority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
945 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
946 * Return the content of the base priority register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
947 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
948 static __INLINE uint32_t __get_BASEPRI(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
949 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
950 register uint32_t __regBasePri __ASM("basepri"); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
951 return(__regBasePri); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
952 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
953 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
954 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
955 * @brief Set the Base Priority value |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
956 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
957 * @param basePri BasePriority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
958 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
959 * Set the base priority register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
960 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
961 static __INLINE void __set_BASEPRI(uint32_t basePri) |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
962 { |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
963 register uint32_t __regBasePri __ASM("basepri"); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
964 __regBasePri = (basePri & 0xff); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
965 } |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
966 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
967 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
968 * @brief Return the Priority Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
969 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
970 * @return PriMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
971 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
972 * Return state of the priority mask bit from the priority mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
973 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
974 static __INLINE uint32_t __get_PRIMASK(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
975 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
976 register uint32_t __regPriMask __ASM("primask"); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
977 return(__regPriMask); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
978 } |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
979 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
980 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
981 * @brief Set the Priority Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
982 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
983 * @param priMask PriMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
984 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
985 * Set the priority mask bit in the priority mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
986 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
987 static __INLINE void __set_PRIMASK(uint32_t priMask) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
988 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
989 register uint32_t __regPriMask __ASM("primask"); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
990 __regPriMask = (priMask); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
991 } |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
992 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
993 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
994 * @brief Return the Fault Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
995 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
996 * @return FaultMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
997 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
998 * Return the content of the fault mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
999 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1000 static __INLINE uint32_t __get_FAULTMASK(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1001 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1002 register uint32_t __regFaultMask __ASM("faultmask"); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1003 return(__regFaultMask); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1004 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1005 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1006 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1007 * @brief Set the Fault Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1008 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1009 * @param faultMask faultMask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1010 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1011 * Set the fault mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1012 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1013 static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1014 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1015 register uint32_t __regFaultMask __ASM("faultmask"); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1016 __regFaultMask = (faultMask & 1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1017 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1018 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1019 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1020 * @brief Return the Control Register value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1021 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1022 * @return Control value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1023 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1024 * Return the content of the control register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1025 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1026 static __INLINE uint32_t __get_CONTROL(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1027 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1028 register uint32_t __regControl __ASM("control"); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1029 return(__regControl); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1030 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1031 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1032 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1033 * @brief Set the Control Register value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1034 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1035 * @param control Control value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1036 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1037 * Set the control register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1038 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1039 static __INLINE void __set_CONTROL(uint32_t control) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1040 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1041 register uint32_t __regControl __ASM("control"); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1042 __regControl = control; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1043 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1044 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1045 #endif /* __ARMCC_VERSION */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1046 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1047 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1048 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1049 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1050 /* IAR iccarm specific functions */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1051 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1052 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1053 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1054 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1055 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1056 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1057 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1058 #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1059 static __INLINE void __WFI() { __ASM ("wfi"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1060 static __INLINE void __WFE() { __ASM ("wfe"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1061 static __INLINE void __SEV() { __ASM ("sev"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1062 static __INLINE void __CLREX() { __ASM ("clrex"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1063 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1064 /* intrinsic void __ISB(void) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1065 /* intrinsic void __DSB(void) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1066 /* intrinsic void __DMB(void) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1067 /* intrinsic void __set_PRIMASK(); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1068 /* intrinsic void __get_PRIMASK(); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1069 /* intrinsic void __set_FAULTMASK(); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1070 /* intrinsic void __get_FAULTMASK(); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1071 /* intrinsic uint32_t __REV(uint32_t value); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1072 /* intrinsic uint32_t __REVSH(uint32_t value); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1073 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1074 /* intrinsic unsigned long __LDREX(unsigned long *); */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1075 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1076 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1077 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1078 * @brief Return the Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1079 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1080 * @return ProcessStackPointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1081 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1082 * Return the actual process stack pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1083 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1084 extern uint32_t __get_PSP(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1085 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1086 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1087 * @brief Set the Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1088 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1089 * @param topOfProcStack Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1090 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1091 * Assign the value ProcessStackPointer to the MSP |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1092 * (process stack pointer) Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1093 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1094 extern void __set_PSP(uint32_t topOfProcStack); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1095 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1096 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1097 * @brief Return the Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1098 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1099 * @return Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1100 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1101 * Return the current value of the MSP (main stack pointer) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1102 * Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1103 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1104 extern uint32_t __get_MSP(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1105 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1106 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1107 * @brief Set the Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1108 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1109 * @param topOfMainStack Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1110 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1111 * Assign the value mainStackPointer to the MSP |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1112 * (main stack pointer) Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1113 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1114 extern void __set_MSP(uint32_t topOfMainStack); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1115 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1116 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1117 * @brief Reverse byte order in unsigned short value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1118 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1119 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1120 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1121 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1122 * Reverse byte order in unsigned short value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1123 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1124 extern uint32_t __REV16(uint16_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1125 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1126 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1127 * @brief Reverse bit order of value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1128 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1129 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1130 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1131 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1132 * Reverse bit order of value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1133 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1134 extern uint32_t __RBIT(uint32_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1135 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1136 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1137 * @brief LDR Exclusive (8 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1138 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1139 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1140 * @return value of (*address) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1141 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1142 * Exclusive LDR command for 8 bit values) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1143 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1144 extern uint8_t __LDREXB(uint8_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1145 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1146 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1147 * @brief LDR Exclusive (16 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1148 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1149 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1150 * @return value of (*address) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1151 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1152 * Exclusive LDR command for 16 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1153 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1154 extern uint16_t __LDREXH(uint16_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1155 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1156 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1157 * @brief LDR Exclusive (32 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1158 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1159 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1160 * @return value of (*address) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1161 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1162 * Exclusive LDR command for 32 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1163 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1164 extern uint32_t __LDREXW(uint32_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1165 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1166 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1167 * @brief STR Exclusive (8 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1168 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1169 * @param value value to store |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1170 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1171 * @return successful / failed |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1172 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1173 * Exclusive STR command for 8 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1174 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1175 extern uint32_t __STREXB(uint8_t value, uint8_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1176 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1177 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1178 * @brief STR Exclusive (16 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1179 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1180 * @param value value to store |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1181 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1182 * @return successful / failed |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1183 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1184 * Exclusive STR command for 16 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1185 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1186 extern uint32_t __STREXH(uint16_t value, uint16_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1187 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1188 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1189 * @brief STR Exclusive (32 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1190 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1191 * @param value value to store |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1192 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1193 * @return successful / failed |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1194 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1195 * Exclusive STR command for 32 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1196 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1197 extern uint32_t __STREXW(uint32_t value, uint32_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1198 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1199 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1200 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1201 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1202 /* GNU gcc specific functions */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1203 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1204 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1205 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1206 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1207 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1208 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1209 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1210 static __INLINE void __NOP() { __ASM volatile ("nop"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1211 static __INLINE void __WFI() { __ASM volatile ("wfi"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1212 static __INLINE void __WFE() { __ASM volatile ("wfe"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1213 static __INLINE void __SEV() { __ASM volatile ("sev"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1214 static __INLINE void __ISB() { __ASM volatile ("isb"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1215 static __INLINE void __DSB() { __ASM volatile ("dsb"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1216 static __INLINE void __DMB() { __ASM volatile ("dmb"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1217 static __INLINE void __CLREX() { __ASM volatile ("clrex"); } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1218 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1219 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1220 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1221 * @brief Return the Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1222 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1223 * @return ProcessStackPointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1224 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1225 * Return the actual process stack pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1226 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1227 extern uint32_t __get_PSP(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1228 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1229 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1230 * @brief Set the Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1231 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1232 * @param topOfProcStack Process Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1233 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1234 * Assign the value ProcessStackPointer to the MSP |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1235 * (process stack pointer) Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1236 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1237 extern void __set_PSP(uint32_t topOfProcStack); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1238 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1239 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1240 * @brief Return the Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1241 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1242 * @return Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1243 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1244 * Return the current value of the MSP (main stack pointer) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1245 * Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1246 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1247 extern uint32_t __get_MSP(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1248 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1249 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1250 * @brief Set the Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1251 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1252 * @param topOfMainStack Main Stack Pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1253 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1254 * Assign the value mainStackPointer to the MSP |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1255 * (main stack pointer) Cortex processor register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1256 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1257 extern void __set_MSP(uint32_t topOfMainStack); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1258 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1259 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1260 * @brief Return the Base Priority value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1261 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1262 * @return BasePriority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1263 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1264 * Return the content of the base priority register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1265 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1266 extern uint32_t __get_BASEPRI(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1267 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1268 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1269 * @brief Set the Base Priority value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1270 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1271 * @param basePri BasePriority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1272 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1273 * Set the base priority register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1274 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1275 extern void __set_BASEPRI(uint32_t basePri); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1276 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1277 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1278 * @brief Return the Priority Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1279 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1280 * @return PriMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1281 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1282 * Return state of the priority mask bit from the priority mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1283 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1284 extern uint32_t __get_PRIMASK(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1285 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1286 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1287 * @brief Set the Priority Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1288 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1289 * @param priMask PriMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1290 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1291 * Set the priority mask bit in the priority mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1292 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1293 extern void __set_PRIMASK(uint32_t priMask); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1294 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1295 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1296 * @brief Return the Fault Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1297 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1298 * @return FaultMask |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1299 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1300 * Return the content of the fault mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1301 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1302 extern uint32_t __get_FAULTMASK(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1303 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1304 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1305 * @brief Set the Fault Mask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1306 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1307 * @param faultMask faultMask value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1308 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1309 * Set the fault mask register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1310 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1311 extern void __set_FAULTMASK(uint32_t faultMask); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1312 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1313 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1314 * @brief Return the Control Register value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1315 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1316 * @return Control value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1317 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1318 * Return the content of the control register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1319 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1320 extern uint32_t __get_CONTROL(void); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1321 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1322 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1323 * @brief Set the Control Register value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1324 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1325 * @param control Control value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1326 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1327 * Set the control register |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1328 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1329 extern void __set_CONTROL(uint32_t control); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1330 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1331 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1332 * @brief Reverse byte order in integer value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1333 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1334 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1335 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1336 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1337 * Reverse byte order in integer value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1338 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1339 extern uint32_t __REV(uint32_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1340 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1341 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1342 * @brief Reverse byte order in unsigned short value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1343 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1344 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1345 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1346 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1347 * Reverse byte order in unsigned short value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1348 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1349 extern uint32_t __REV16(uint16_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1350 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1351 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1352 * @brief Reverse byte order in signed short value with sign extension to integer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1353 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1354 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1355 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1356 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1357 * Reverse byte order in signed short value with sign extension to integer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1358 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1359 extern int32_t __REVSH(int16_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1360 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1361 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1362 * @brief Reverse bit order of value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1363 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1364 * @param value value to reverse |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1365 * @return reversed value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1366 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1367 * Reverse bit order of value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1368 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1369 extern uint32_t __RBIT(uint32_t value); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1370 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1371 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1372 * @brief LDR Exclusive (8 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1373 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1374 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1375 * @return value of (*address) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1376 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1377 * Exclusive LDR command for 8 bit value |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1378 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1379 extern uint8_t __LDREXB(uint8_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1380 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1381 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1382 * @brief LDR Exclusive (16 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1383 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1384 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1385 * @return value of (*address) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1386 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1387 * Exclusive LDR command for 16 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1388 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1389 extern uint16_t __LDREXH(uint16_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1390 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1391 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1392 * @brief LDR Exclusive (32 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1393 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1394 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1395 * @return value of (*address) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1396 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1397 * Exclusive LDR command for 32 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1398 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1399 extern uint32_t __LDREXW(uint32_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1400 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1401 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1402 * @brief STR Exclusive (8 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1403 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1404 * @param value value to store |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1405 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1406 * @return successful / failed |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1407 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1408 * Exclusive STR command for 8 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1409 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1410 extern uint32_t __STREXB(uint8_t value, uint8_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1411 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1412 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1413 * @brief STR Exclusive (16 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1414 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1415 * @param value value to store |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1416 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1417 * @return successful / failed |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1418 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1419 * Exclusive STR command for 16 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1420 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1421 extern uint32_t __STREXH(uint16_t value, uint16_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1422 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1423 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1424 * @brief STR Exclusive (32 bit) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1425 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1426 * @param value value to store |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1427 * @param *addr address pointer |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1428 * @return successful / failed |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1429 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1430 * Exclusive STR command for 32 bit values |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1431 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1432 extern uint32_t __STREXW(uint32_t value, uint32_t *addr); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1433 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1434 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1435 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1436 /* TASKING carm specific functions */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1437 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1438 /* |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1439 * The CMSIS functions have been implemented as intrinsics in the compiler. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1440 * Please use "carm -?i" to get an up to date list of all instrinsics, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1441 * Including the CMSIS ones. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1442 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1443 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1444 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1445 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1446 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1447 /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1448 Core Function Interface containing: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1449 - Core NVIC Functions |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1450 - Core SysTick Functions |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1451 - Core Reset Functions |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1452 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1453 /*@{*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1454 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1455 /* ########################## NVIC functions #################################### */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1456 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1457 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1458 * @brief Set the Priority Grouping in NVIC Interrupt Controller |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1459 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1460 * @param PriorityGroup is priority grouping field |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1461 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1462 * Set the priority grouping field using the required unlock sequence. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1463 * The parameter priority_grouping is assigned to the field |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1464 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1465 * In case of a conflict between priority grouping and available |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1466 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1467 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1468 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1469 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1470 uint32_t reg_value; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1471 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1472 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1473 reg_value = SCB->AIRCR; /* read old register configuration */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1474 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1475 reg_value = (reg_value | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1476 (0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1477 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1478 SCB->AIRCR = reg_value; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1479 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1480 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1481 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1482 * @brief Get the Priority Grouping from NVIC Interrupt Controller |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1483 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1484 * @return priority grouping field |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1485 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1486 * Get the priority grouping from NVIC Interrupt Controller. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1487 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1488 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1489 static __INLINE uint32_t NVIC_GetPriorityGrouping(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1490 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1491 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1492 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1493 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1494 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1495 * @brief Enable Interrupt in NVIC Interrupt Controller |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1496 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1497 * @param IRQn The positive number of the external interrupt to enable |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1498 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1499 * Enable a device specific interupt in the NVIC interrupt controller. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1500 * The interrupt number cannot be a negative value. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1501 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1502 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1503 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1504 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1505 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1506 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1507 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1508 * @brief Disable the interrupt line for external interrupt specified |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1509 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1510 * @param IRQn The positive number of the external interrupt to disable |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1511 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1512 * Disable a device specific interupt in the NVIC interrupt controller. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1513 * The interrupt number cannot be a negative value. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1514 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1515 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1516 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1517 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1518 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1519 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1520 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1521 * @brief Read the interrupt pending bit for a device specific interrupt source |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1522 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1523 * @param IRQn The number of the device specifc interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1524 * @return 1 = interrupt pending, 0 = interrupt not pending |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1525 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1526 * Read the pending register in NVIC and return 1 if its status is pending, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1527 * otherwise it returns 0 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1528 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1529 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1530 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1531 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1532 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1533 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1534 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1535 * @brief Set the pending bit for an external interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1536 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1537 * @param IRQn The number of the interrupt for set pending |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1538 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1539 * Set the pending bit for the specified interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1540 * The interrupt number cannot be a negative value. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1541 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1542 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1543 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1544 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1545 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1546 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1547 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1548 * @brief Clear the pending bit for an external interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1549 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1550 * @param IRQn The number of the interrupt for clear pending |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1551 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1552 * Clear the pending bit for the specified interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1553 * The interrupt number cannot be a negative value. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1554 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1555 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1556 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1557 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1558 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1559 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1560 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1561 * @brief Read the active bit for an external interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1562 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1563 * @param IRQn The number of the interrupt for read active bit |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1564 * @return 1 = interrupt active, 0 = interrupt not active |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1565 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1566 * Read the active register in NVIC and returns 1 if its status is active, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1567 * otherwise it returns 0. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1568 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1569 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1570 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1571 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1572 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1573 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1574 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1575 * @brief Set the priority for an interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1576 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1577 * @param IRQn The number of the interrupt for set priority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1578 * @param priority The priority to set |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1579 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1580 * Set the priority for the specified interrupt. The interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1581 * number can be positive to specify an external (device specific) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1582 * interrupt, or negative to specify an internal (core) interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1583 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1584 * Note: The priority cannot be set for every core interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1585 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1586 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1587 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1588 if(IRQn < 0) { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1589 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1590 else { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1591 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1592 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1593 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1594 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1595 * @brief Read the priority for an interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1596 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1597 * @param IRQn The number of the interrupt for get priority |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1598 * @return The priority for the interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1599 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1600 * Read the priority for the specified interrupt. The interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1601 * number can be positive to specify an external (device specific) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1602 * interrupt, or negative to specify an internal (core) interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1603 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1604 * The returned priority value is automatically aligned to the implemented |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1605 * priority bits of the microcontroller. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1606 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1607 * Note: The priority cannot be set for every core interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1608 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1609 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1610 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1611 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1612 if(IRQn < 0) { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1613 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1614 else { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1615 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1616 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1617 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1618 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1619 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1620 * @brief Encode the priority for an interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1621 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1622 * @param PriorityGroup The used priority group |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1623 * @param PreemptPriority The preemptive priority value (starting from 0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1624 * @param SubPriority The sub priority value (starting from 0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1625 * @return The encoded priority for the interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1626 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1627 * Encode the priority for an interrupt with the given priority group, |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1628 * preemptive priority value and sub priority value. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1629 * In case of a conflict between priority grouping and available |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1630 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1631 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1632 * The returned priority value can be used for NVIC_SetPriority(...) function |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1633 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1634 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1635 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1636 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1637 uint32_t PreemptPriorityBits; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1638 uint32_t SubPriorityBits; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1639 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1640 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1641 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1642 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1643 return ( |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1644 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1645 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1646 ); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1647 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1648 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1649 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1650 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1651 * @brief Decode the priority of an interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1652 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1653 * @param Priority The priority for the interrupt |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1654 * @param PriorityGroup The used priority group |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1655 * @param pPreemptPriority The preemptive priority value (starting from 0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1656 * @param pSubPriority The sub priority value (starting from 0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1657 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1658 * Decode an interrupt priority value with the given priority group to |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1659 * preemptive priority value and sub priority value. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1660 * In case of a conflict between priority grouping and available |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1661 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1662 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1663 * The priority value can be retrieved with NVIC_GetPriority(...) function |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1664 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1665 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1666 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1667 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1668 uint32_t PreemptPriorityBits; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1669 uint32_t SubPriorityBits; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1670 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1671 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1672 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1673 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1674 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1675 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1676 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1677 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1678 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1679 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1680 /* ################################## SysTick function ############################################ */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1681 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1682 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1683 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1684 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1685 * @brief Initialize and start the SysTick counter and its interrupt. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1686 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1687 * @param ticks number of ticks between two interrupts |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1688 * @return 1 = failed, 0 = successful |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1689 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1690 * Initialise the system tick timer and its interrupt and start the |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1691 * system tick timer / counter in free running mode to generate |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1692 * periodical interrupts. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1693 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1694 static __INLINE uint32_t SysTick_Config(uint32_t ticks) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1695 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1696 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1697 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1698 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1699 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1700 SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1701 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1702 SysTick_CTRL_TICKINT_Msk | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1703 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1704 return (0); /* Function successful */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1705 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1706 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1707 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1708 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1709 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1710 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1711 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1712 /* ################################## Reset function ############################################ */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1713 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1714 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1715 * @brief Initiate a system reset request. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1716 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1717 * Initiate a system reset request to reset the MCU |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1718 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1719 static __INLINE void NVIC_SystemReset(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1720 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1721 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1722 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1723 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1724 __DSB(); /* Ensure completion of memory access */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1725 while(1); /* wait until reset */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1726 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1727 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1728 /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1729 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1730 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1731 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1732 /* ##################################### Debug In/Output function ########################################### */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1733 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1734 /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1735 Core Debug Interface containing: |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1736 - Core Debug Receive / Transmit Functions |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1737 - Core Debug Defines |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1738 - Core Debug Variables |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1739 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1740 /*@{*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1741 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1742 extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1743 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1744 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1745 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1746 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1747 * @brief Outputs a character via the ITM channel 0 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1748 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1749 * @param ch character to output |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1750 * @return character to output |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1751 * |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1752 * The function outputs a character via the ITM channel 0. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1753 * The function returns when no debugger is connected that has booked the output. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
1754 * It is blocking when a debugger is connected, but the previous character send is not transmitted. |
c59513fd84fb
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1755 */ |
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1756 static __INLINE uint32_t ITM_SendChar (uint32_t ch) |
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1757 { |
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1758 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ |
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Initial commit of STM32 test code.
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1759 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ |
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Initial commit of STM32 test code.
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1760 (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ |
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|
1761 { |
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Initial commit of STM32 test code.
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1762 while (ITM->PORT[0].u32 == 0); |
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Initial commit of STM32 test code.
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1763 ITM->PORT[0].u8 = (uint8_t) ch; |
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Initial commit of STM32 test code.
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1764 } |
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Initial commit of STM32 test code.
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1765 return (ch); |
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1766 } |
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Initial commit of STM32 test code.
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1767 |
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1768 |
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1769 /** |
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1770 * @brief Inputs a character via variable ITM_RxBuffer |
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1771 * |
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1772 * @return received character, -1 = no character received |
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1773 * |
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1774 * The function inputs a character via variable ITM_RxBuffer. |
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1775 * The function returns when no debugger is connected that has booked the output. |
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1776 * It is blocking when a debugger is connected, but the previous character send is not transmitted. |
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Initial commit of STM32 test code.
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|
1777 */ |
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1778 static __INLINE int ITM_ReceiveChar (void) { |
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1779 int ch = -1; /* no character available */ |
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1780 |
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1781 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
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1782 ch = ITM_RxBuffer; |
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1783 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
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1784 } |
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|
1785 |
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1786 return (ch); |
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1787 } |
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1788 |
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1789 |
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1790 /** |
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1791 * @brief Check if a character via variable ITM_RxBuffer is available |
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1792 * |
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1793 * @return 1 = character available, 0 = no character available |
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1794 * |
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1795 * The function checks variable ITM_RxBuffer whether a character is available or not. |
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1796 * The function returns '1' if a character is available and '0' if no character is available. |
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1797 */ |
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1798 static __INLINE int ITM_CheckChar (void) { |
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1799 |
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1800 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
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1801 return (0); /* no character available */ |
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1802 } else { |
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1803 return (1); /* character available */ |
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1804 } |
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1805 } |
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1806 |
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1807 /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ |
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1808 |
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1809 |
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1810 #ifdef __cplusplus |
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1811 } |
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1812 #endif |
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1813 |
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1814 /*@}*/ /* end of group CMSIS_CM3_core_definitions */ |
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1815 |
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1816 #endif /* __CM3_CORE_H__ */ |
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1817 |
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1818 /*lint -restore */ |