Mercurial > ~darius > hgwebdir.cgi > stm32temp

annotate delay.c @ 71:778adff8b569

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Comment out debug message.
author Daniel O'Connor <darius@dons.net.au>
date Sun, 14 Apr 2013 22:54:10 +0930
parents a38003b97de6
children cecb0506f4b8
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
40
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
1 #include <assert.h>
8
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
2 #include <stdint.h>
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
3 #include "stm32f10x.h"
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
4 #include "delay.h"
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
5
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
6 /* Sleep for nCount usec
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
7 */
8
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
8 void
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
9 delay(uint32_t nCount) {
40
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
10 uint32_t dly, cnt, clk_per_usec, max_dly;
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
11 volatile uint32_t *DWT_CYCCNT = (uint32_t *)0xe0001004;
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
12
40
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
13 __disable_irq();
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
14
40
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
15 #ifdef SYSCLK_FREQ_72MHz
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
16 clk_per_usec = 72;
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
17 max_dly = (1<<31) / clk_per_usec; /* Really half the maximum (still ~30 seconds at 72MHz) */
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
18 #else
40
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
19 #error "Unknown clock frequency"
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
20 #endif
40
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
21 assert(nCount < max_dly);
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
22
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
23 cnt = *DWT_CYCCNT; /* Get current cycle count */
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
24 dly = nCount * clk_per_usec;
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
25 dly += cnt; /* Compute cycle count to stop at */
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
26 if (dly < cnt)
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
27 /* Stop count wrapped, wait until the counter wraps around */
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
28 while (*DWT_CYCCNT > cnt)
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
29 ;
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
30 /* Wait until we get to the stop count */
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
31 while (*DWT_CYCCNT < dly)
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
32 ;
a38003b97de6 Use debug cycle counter to handle delays.
Daniel O'Connor <darius@dons.net.au>
parents: 14
diff changeset
33
14
891841f5f785 Fix delay() to be accurate as measured on the cro.
Daniel O'Connor <darius@dons.net.au>
parents: 8
diff changeset
34 __enable_irq();
8
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
35 }
58d76cf522ff Split out code into separate files.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
36