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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/main.c @ 8:58d76cf522ff

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Split out code into separate files.
author Daniel O'Connor <darius@dons.net.au>
date Sat, 04 Feb 2012 13:29:31 +1030
parents c59513fd84fb
children
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1 /**
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2 ******************************************************************************
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3 * @file TIM/DMA/main.c
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4 * @author MCD Application Team
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5 * @version V3.5.0
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6 * @date 08-April-2011
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7 * @brief Main program body
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 *
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18 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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19 ******************************************************************************
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20 */
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21
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22 /* Includes ------------------------------------------------------------------*/
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23 #include "stm32f10x.h"
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24
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25 /** @addtogroup STM32F10x_StdPeriph_Examples
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26 * @{
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27 */
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28
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29 /** @addtogroup TIM_DMA
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30 * @{
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31 */
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32
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33 /* Private typedef -----------------------------------------------------------*/
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34 /* Private define ------------------------------------------------------------*/
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35 #define TIM1_CCR3_Address 0x40012C3C
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36
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37 /* Private macro -------------------------------------------------------------*/
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38 /* Private variables ---------------------------------------------------------*/
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39 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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40 TIM_OCInitTypeDef TIM_OCInitStructure;
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41 uint16_t SRC_Buffer[3] = {0, 0, 0};
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42 uint16_t TimerPeriod = 0;
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43
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44 /* Private function prototypes -----------------------------------------------*/
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45 void RCC_Configuration(void);
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46 void GPIO_Configuration(void);
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47 void DMA_Configuration(void);
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48
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49 /* Private functions ---------------------------------------------------------*/
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50
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51 /**
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52 * @brief Main program
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53 * @param None
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54 * @retval None
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55 */
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56 int main(void)
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57 {
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58 /*!< At this stage the microcontroller clock setting is already configured,
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59 this is done through SystemInit() function which is called from startup
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60 file (startup_stm32f10x_xx.s) before to branch to application main.
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61 To reconfigure the default setting of SystemInit() function, refer to
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62 system_stm32f10x.c file
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63 */
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64
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65 /* System Clocks Configuration */
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66 RCC_Configuration();
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67
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68 /* GPIO Configuration */
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69 GPIO_Configuration();
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70
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71 /* DMA Configuration */
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72 DMA_Configuration();
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73
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74 /* TIM1 DMA Transfer example -------------------------------------------------
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75 TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
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76 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
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77 and Connectivity line devices and to 24 MHz for Low-Density Value line and
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78 Medium-Density Value line devices.
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79
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80 The objective is to configure TIM1 channel 3 to generate complementary PWM
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81 signal with a frequency equal to 17.57 KHz:
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82 - TIM1_Period = (SystemCoreClock / 17570) - 1
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83 and a variable duty cycle that is changed by the DMA after a specific number of
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84 Update DMA request.
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85
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86 The number of this repetitive requests is defined by the TIM1 Repetition counter,
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87 each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new
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88 value defined by the SRC_Buffer .
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89 -----------------------------------------------------------------------------*/
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90 /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
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91 TimerPeriod = (SystemCoreClock / 17570 ) - 1;
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92 /* Compute CCR1 value to generate a duty cycle at 50% */
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93 SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
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94 /* Compute CCR1 value to generate a duty cycle at 37.5% */
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95 SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
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96 /* Compute CCR1 value to generate a duty cycle at 25% */
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97 SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
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98
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99 /* TIM1 Peripheral Configuration --------------------------------------------*/
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100 /* Time Base configuration */
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101 TIM_TimeBaseStructure.TIM_Prescaler = 0;
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102 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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103 TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
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104 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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105 TIM_TimeBaseStructure.TIM_RepetitionCounter = 2;
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106
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107 TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
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108
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109 /* Channel 3 Configuration in PWM mode */
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110 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
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111 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
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112 TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
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113 TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
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114 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
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115 TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
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116 TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
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117 TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
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118
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119 TIM_OC3Init(TIM1, &TIM_OCInitStructure);
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120
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121 /* TIM1 Update DMA Request enable */
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122 TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
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123
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124 /* TIM1 counter enable */
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125 TIM_Cmd(TIM1, ENABLE);
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126
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127 /* Main Output Enable */
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128 TIM_CtrlPWMOutputs(TIM1, ENABLE);
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129
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130 while (1)
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131 {}
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132 }
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133
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134 /**
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135 * @brief Configures the different system clocks.
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136 * @param None
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137 * @retval None
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138 */
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139 void RCC_Configuration(void)
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140 {
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141 /* TIM1, GPIOA and GPIOB clock enable */
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142 RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA |
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143 RCC_APB2Periph_GPIOB, ENABLE);
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144 /* DMA clock enable */
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145 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
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146 }
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147
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148 /**
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149 * @brief Configure the TIM1 Pins.
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150 * @param None
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151 * @retval None
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152 */
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153 void GPIO_Configuration(void)
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154 {
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155 GPIO_InitTypeDef GPIO_InitStructure;
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156
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157 /* GPIOA Configuration: Channel 3 as alternate function push-pull */
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158 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
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159 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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160 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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161 GPIO_Init(GPIOA, &GPIO_InitStructure);
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162
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163 /* GPIOB Configuration: Channel 3N as alternate function push-pull */
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164 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
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165 GPIO_Init(GPIOB, &GPIO_InitStructure);
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166 }
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167
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168 /**
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169 * @brief Configures the DMA.
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170 * @param None
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171 * @retval None
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172 */
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173 void DMA_Configuration(void)
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174 {
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175 DMA_InitTypeDef DMA_InitStructure;
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176
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177 /* DMA1 Channel5 Config */
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178 DMA_DeInit(DMA1_Channel5);
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179
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180 DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR3_Address;
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181 DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
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182 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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183 DMA_InitStructure.DMA_BufferSize = 3;
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184 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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185 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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186 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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187 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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188 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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189 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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190 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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191
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192 DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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193
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194 /* DMA1 Channel5 enable */
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195 DMA_Cmd(DMA1_Channel5, ENABLE);
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196 }
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197
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198 #ifdef USE_FULL_ASSERT
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199
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200 /**
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201 * @brief Reports the name of the source file and the source line number
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202 * where the assert_param error has occurred.
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203 * @param file: pointer to the source file name
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204 * @param line: assert_param error line source number
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205 * @retval None
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206 */
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207 void assert_failed(uint8_t* file, uint32_t line)
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208 {
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209 /* User can add his own implementation to report the file name and line number,
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210 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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211
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212 while (1)
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213 {}
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214 }
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215
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216 #endif
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217
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218 /**
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219 * @}
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220 */
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221
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222 /**
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223 * @}
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224 */
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225
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226 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/