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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt @ 8:58d76cf522ff

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Split out code into separate files.
author Daniel O'Connor <darius@dons.net.au>
date Sat, 04 Feb 2012 13:29:31 +1030
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1 /**
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2 @page TIM_Cascade_Synchro TIM Cascade Synchro example
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3
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4 @verbatim
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5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
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6 * @file TIM/Cascade_Synchro/readme.txt
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7 * @author MCD Application Team
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8 * @version V3.5.0
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9 * @date 08-April-2011
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10 * @brief Description of the TIM Cascade Synchro example.
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11 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 ******************************************************************************
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19 @endverbatim
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20
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21 @par Example Description
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22
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23 This example shows how to synchronize TIM peripherals in cascade mode.
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24 In this example three timers are used:
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25
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26 Timers synchronisation in cascade mode:
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27
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28 1/TIM2 is configured as Master Timer:
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29 - PWM Mode is used
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30 - The TIM2 Update event is used as Trigger Output
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31
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32 2/TIM3 is slave for TIM2 and Master for TIM4,
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33 - PWM Mode is used
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34 - The ITR1(TIM2) is used as input trigger
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35 - Gated mode is used, so start and stop of slave counter
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36 are controlled by the Master trigger output signal(TIM2 update event).
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37 - The TIM3 Update event is used as Trigger Output.
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38
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39 3/TIM4 is slave for TIM3,
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40 - PWM Mode is used
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41 - The ITR2(TIM3) is used as input trigger
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42 - Gated mode is used, so start and stop of slave counter are controlled by the
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43 Master trigger output signal(TIM3 update event).
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44
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45 o For Low-density, Medium-density, High-density and Connectivity line devices:
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46 The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
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47
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48 The Master Timer TIM2 is running at TIM2 frequency :
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49 TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 281.250 KHz
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50 and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.
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51
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52 The TIM3 is running at:
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53 (TIM2 frequency)/ (TIM3 period + 1) = 70.312 KHz and a duty cycle equal
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54 to TIM3_CCR1/(TIM3_ARR + 1) = 25%
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55
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56 The TIM4 is running at:
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57 (TIM3 frequency)/ (TIM4 period + 1) = 17.578 Hz and a duty cycle equal
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58 to TIM4_CCR1/(TIM4_ARR + 1) = 25%
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59
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60 o For Low-Density Value line, Medium-Density and High-Density Value line devices:
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61 The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
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62 So TIM2 frequency = 93.750 KHz,
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63 TIM3 is running at 23.437 KHz,
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64 and TIM4 is running at 5.85 KHz
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65
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66 @par Directory contents
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67
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68 - TIM/Cascade_Synchro/stm32f10x_conf.h Library Configuration file
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69 - TIM/Cascade_Synchro/stm32f10x_it.c Interrupt handlers
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70 - TIM/Cascade_Synchro/stm32f10x_it.h Interrupt handlers header file
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71 - TIM/Cascade_Synchro/main.c Main program
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72 - TIM/Cascade_Synchro/system_stm32f10x.c STM32F10x system source file
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73
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74 @par Hardware and Software environment
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75
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76 - This example runs on STM32F10x Connectivity line, High-Density, High-Density
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77 Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
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78 and Low-Density Value line Devices.
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79
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80 - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
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81 Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line),
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82 STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density)
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83 evaluation boards and can be easily tailored to any other supported device
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84 and development board.
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85
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86 - STM3210C-EVAL Set-up
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87 - Connect the following pins to an oscilloscope to monitor the different
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88 waveforms:
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89 - TIM2 CH1 (PA.00)
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90 - TIM3 CH1 (PC.06) Remapped pin
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91 - TIM4 CH1 (PB.06)
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92
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93 - STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up
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94 - Connect the following pins to an oscilloscope to monitor the different
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95 waveforms:
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96 - TIM2 CH1 (PA.00)
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97 - TIM3 CH1 (PA.06)
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98 - TIM4 CH1 (PB.06)
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99
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100 @par How to use it ?
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101
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102 In order to make the program work, you must do the following :
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103 - Copy all source files from this example folder to the template folder under
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104 Project\STM32F10x_StdPeriph_Template
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105 - Open your preferred toolchain
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106 - Rebuild all files and load your image into target memory
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107 - Run the example
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108
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109 @note
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110 - Low-density Value line devices are STM32F100xx microcontrollers where the
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111 Flash memory density ranges between 16 and 32 Kbytes.
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112 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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113 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
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114 - Medium-density Value line devices are STM32F100xx microcontrollers where
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115 the Flash memory density ranges between 64 and 128 Kbytes.
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116 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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117 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
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118 - High-density Value line devices are STM32F100xx microcontrollers where
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119 the Flash memory density ranges between 256 and 512 Kbytes.
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120 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
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121 the Flash memory density ranges between 256 and 512 Kbytes.
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122 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
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123 the Flash memory density ranges between 512 and 1024 Kbytes.
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124 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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125
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126 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
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127 */