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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c @ 48:2f336d212c74
Ignore more emacs crap.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Wed, 03 Apr 2013 23:33:47 +1030 |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm3210e_eval_fsmc_nor.c |
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4 * @author MCD Application Team |
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5 * @version V4.5.0 |
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6 * @date 07-March-2011 |
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7 * @brief This file provides a set of functions needed to drive the M29W128FL, |
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8 * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board. |
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9 ****************************************************************************** |
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10 * @attention |
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11 * |
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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18 * |
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19 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
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20 ****************************************************************************** |
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21 */ |
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22 |
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23 /* Includes ------------------------------------------------------------------*/ |
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24 #include "stm3210e_eval_fsmc_nor.h" |
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25 |
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26 /** @addtogroup Utilities |
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27 * @{ |
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28 */ |
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29 |
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30 /** @addtogroup STM32_EVAL |
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31 * @{ |
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32 */ |
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33 |
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34 /** @addtogroup STM3210E_EVAL |
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35 * @{ |
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36 */ |
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37 |
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38 /** @addtogroup STM3210E_EVAL_FSMC_NOR |
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39 * @brief This file provides a set of functions needed to drive the M29W128FL, |
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40 * M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board. |
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41 * @{ |
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42 */ |
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43 |
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44 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Types |
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45 * @{ |
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46 */ |
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47 /** |
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48 * @} |
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49 */ |
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50 |
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51 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Defines |
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52 * @{ |
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53 */ |
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54 /** |
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55 * @brief FSMC Bank 1 NOR/SRAM2 |
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56 */ |
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57 #define Bank1_NOR2_ADDR ((uint32_t)0x64000000) |
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58 |
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59 /* Delay definition */ |
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60 #define BlockErase_Timeout ((uint32_t)0x00A00000) |
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61 #define ChipErase_Timeout ((uint32_t)0x30000000) |
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62 #define Program_Timeout ((uint32_t)0x00001400) |
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63 /** |
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64 * @} |
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65 */ |
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66 |
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67 |
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68 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Macros |
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69 * @{ |
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70 */ |
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71 #define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A))) |
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72 #define NOR_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data)) |
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73 /** |
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74 * @} |
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75 */ |
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76 |
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77 |
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78 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Variables |
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79 * @{ |
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80 */ |
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81 /** |
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82 * @} |
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83 */ |
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84 |
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85 |
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86 /** @defgroupSTM3210E_EVAL_FSMC_NOR_Private_Function_Prototypes |
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87 * @{ |
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88 */ |
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89 /** |
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90 * @} |
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91 */ |
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92 |
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93 |
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94 /** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Functions |
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95 * @{ |
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96 */ |
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97 |
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98 /** |
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99 * @brief Configures the FSMC and GPIOs to interface with the NOR memory. |
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100 * This function must be called before any write/read operation |
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101 * on the NOR. |
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102 * @param None |
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103 * @retval None |
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104 */ |
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105 void NOR_Init(void) |
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106 { |
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107 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; |
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108 FSMC_NORSRAMTimingInitTypeDef p; |
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109 GPIO_InitTypeDef GPIO_InitStructure; |
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110 |
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111 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | |
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112 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE); |
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113 |
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114 /*-- GPIO Configuration ------------------------------------------------------*/ |
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115 /*!< NOR Data lines configuration */ |
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116 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | |
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117 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; |
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118 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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119 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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120 GPIO_Init(GPIOD, &GPIO_InitStructure); |
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121 |
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122 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | |
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123 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | |
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124 GPIO_Pin_14 | GPIO_Pin_15; |
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125 GPIO_Init(GPIOE, &GPIO_InitStructure); |
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126 |
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127 /*!< NOR Address lines configuration */ |
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128 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | |
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129 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | |
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130 GPIO_Pin_14 | GPIO_Pin_15; |
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131 GPIO_Init(GPIOF, &GPIO_InitStructure); |
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132 |
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133 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | |
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134 GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; |
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135 GPIO_Init(GPIOG, &GPIO_InitStructure); |
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136 |
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137 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; |
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138 GPIO_Init(GPIOD, &GPIO_InitStructure); |
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139 |
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140 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6; |
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141 GPIO_Init(GPIOE, &GPIO_InitStructure); |
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142 |
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143 /*!< NOE and NWE configuration */ |
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144 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; |
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145 GPIO_Init(GPIOD, &GPIO_InitStructure); |
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146 |
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147 /*!< NE2 configuration */ |
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148 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; |
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149 GPIO_Init(GPIOG, &GPIO_InitStructure); |
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150 |
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151 /*!< Configure PD6 for NOR memory Ready/Busy signal */ |
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152 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; |
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153 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; |
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154 GPIO_Init(GPIOD, &GPIO_InitStructure); |
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155 |
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156 /*-- FSMC Configuration ----------------------------------------------------*/ |
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157 p.FSMC_AddressSetupTime = 0x02; |
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158 p.FSMC_AddressHoldTime = 0x00; |
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159 p.FSMC_DataSetupTime = 0x05; |
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160 p.FSMC_BusTurnAroundDuration = 0x00; |
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161 p.FSMC_CLKDivision = 0x00; |
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162 p.FSMC_DataLatency = 0x00; |
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163 p.FSMC_AccessMode = FSMC_AccessMode_B; |
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164 |
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165 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; |
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166 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; |
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167 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR; |
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168 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; |
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169 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
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170 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
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171 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
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172 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; |
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173 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
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174 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
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175 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; |
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176 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
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177 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
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178 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; |
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179 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; |
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180 |
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181 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); |
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182 |
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183 /*!< Enable FSMC Bank1_NOR Bank */ |
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184 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); |
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185 } |
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186 |
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187 /** |
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188 * @brief Reads NOR memory's Manufacturer and Device Code. |
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189 * @param NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the |
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190 * Manufacturer and Device Code. |
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191 * @retval None |
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192 */ |
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193 void NOR_ReadID(NOR_IDTypeDef* NOR_ID) |
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194 { |
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195 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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196 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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197 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090); |
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198 |
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199 NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000); |
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200 NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001); |
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201 NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E); |
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202 NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F); |
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203 } |
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204 |
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205 /** |
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206 * @brief Erases the specified Nor memory block. |
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207 * @param BlockAddr: address of the block to erase. |
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208 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR |
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209 * or NOR_TIMEOUT |
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210 */ |
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211 NOR_Status NOR_EraseBlock(uint32_t BlockAddr) |
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212 { |
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213 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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214 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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215 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080); |
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216 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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217 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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218 NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30); |
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219 |
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220 return (NOR_GetStatus(BlockErase_Timeout)); |
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221 } |
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222 |
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223 /** |
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224 * @brief Erases the entire chip. |
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225 * @param None |
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226 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR |
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227 * or NOR_TIMEOUT |
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228 */ |
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229 NOR_Status NOR_EraseChip(void) |
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230 { |
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231 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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232 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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233 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080); |
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234 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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235 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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236 NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010); |
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237 |
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238 return (NOR_GetStatus(ChipErase_Timeout)); |
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239 } |
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240 |
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241 /** |
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242 * @brief Writes a half-word to the NOR memory. |
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243 * @param WriteAddr: NOR memory internal address to write to. |
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244 * @param Data: Data to write. |
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245 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR |
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246 * or NOR_TIMEOUT |
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247 */ |
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248 NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data) |
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249 { |
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250 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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251 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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252 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0); |
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253 NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data); |
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254 |
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255 return (NOR_GetStatus(Program_Timeout)); |
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256 } |
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257 |
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258 /** |
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259 * @brief Writes a half-word buffer to the FSMC NOR memory. |
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260 * @param pBuffer: pointer to buffer. |
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261 * @param WriteAddr: NOR memory internal address from which the data will be |
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262 * written. |
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263 * @param NumHalfwordToWrite: number of Half words to write. |
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264 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR |
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265 * or NOR_TIMEOUT |
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266 */ |
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267 NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) |
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268 { |
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269 NOR_Status status = NOR_ONGOING; |
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270 |
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271 do |
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272 { |
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273 /*!< Transfer data to the memory */ |
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274 status = NOR_WriteHalfWord(WriteAddr, *pBuffer++); |
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275 WriteAddr = WriteAddr + 2; |
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276 NumHalfwordToWrite--; |
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277 } |
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278 while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0)); |
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279 |
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280 return (status); |
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281 } |
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282 |
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283 /** |
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284 * @brief Writes a half-word buffer to the FSMC NOR memory. This function |
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285 * must be used only with S29GL128P NOR memory. |
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286 * @param pBuffer: pointer to buffer. |
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287 * @param WriteAddr: NOR memory internal address from which the data will be |
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288 * written. |
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289 * @param NumHalfwordToWrite: number of Half words to write. |
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290 * The maximum allowed value is 32 Half words (64 bytes). |
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291 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR |
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292 * or NOR_TIMEOUT |
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293 */ |
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294 NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) |
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295 { |
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296 uint32_t lastloadedaddress = 0x00; |
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297 uint32_t currentaddress = 0x00; |
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298 uint32_t endaddress = 0x00; |
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299 |
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300 /*!< Initialize variables */ |
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301 currentaddress = WriteAddr; |
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302 endaddress = WriteAddr + NumHalfwordToWrite - 1; |
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303 lastloadedaddress = WriteAddr; |
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304 |
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305 /*!< Issue unlock command sequence */ |
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306 NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); |
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307 |
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308 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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309 |
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310 /*!< Write Write Buffer Load Command */ |
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311 NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025); |
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312 NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1)); |
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313 |
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314 /*!< Load Data into NOR Buffer */ |
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315 while(currentaddress <= endaddress) |
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316 { |
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317 /*!< Store last loaded address & data value (for polling) */ |
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318 lastloadedaddress = currentaddress; |
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319 |
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320 NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++); |
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321 currentaddress += 1; |
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322 } |
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323 |
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324 NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29); |
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325 |
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326 return(NOR_GetStatus(Program_Timeout)); |
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327 } |
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328 |
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329 /** |
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330 * @brief Reads a half-word from the NOR memory. |
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331 * @param ReadAddr: NOR memory internal address to read from. |
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332 * @retval Half-word read from the NOR memory |
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333 */ |
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334 uint16_t NOR_ReadHalfWord(uint32_t ReadAddr) |
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335 { |
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336 NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); |
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337 NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); |
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338 NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 ); |
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339 |
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340 return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr))); |
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341 } |
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342 |
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343 /** |
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344 * @brief Reads a block of data from the FSMC NOR memory. |
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345 * @param pBuffer: pointer to the buffer that receives the data read from the |
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346 * NOR memory. |
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347 * @param ReadAddr: NOR memory internal address to read from. |
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348 * @param NumHalfwordToRead : number of Half word to read. |
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349 * @retval None |
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350 */ |
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351 void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) |
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352 { |
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353 NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA); |
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354 NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055); |
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355 NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0); |
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356 |
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357 for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */ |
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358 { |
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359 /*!< Read a Halfword from the NOR */ |
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360 *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)); |
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361 ReadAddr = ReadAddr + 2; |
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362 } |
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363 } |
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364 |
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365 /** |
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366 * @brief Returns the NOR memory to Read mode. |
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367 * @param None |
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368 * @retval NOR_SUCCESS |
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369 */ |
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370 NOR_Status NOR_ReturnToReadMode(void) |
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371 { |
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372 NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); |
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373 |
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374 return (NOR_SUCCESS); |
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375 } |
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376 |
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377 /** |
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378 * @brief Returns the NOR memory to Read mode and resets the errors in the NOR |
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379 * memory Status Register. |
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380 * @param None |
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381 * @retval NOR_SUCCESS |
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382 */ |
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383 NOR_Status NOR_Reset(void) |
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384 { |
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385 NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); |
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386 NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); |
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387 NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); |
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388 |
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389 return (NOR_SUCCESS); |
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390 } |
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391 |
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392 /** |
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393 * @brief Returns the NOR operation status. |
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394 * @param Timeout: NOR progamming Timeout |
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395 * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR |
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396 * or NOR_TIMEOUT |
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397 */ |
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398 NOR_Status NOR_GetStatus(uint32_t Timeout) |
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399 { |
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400 uint16_t val1 = 0x00, val2 = 0x00; |
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401 NOR_Status status = NOR_ONGOING; |
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402 uint32_t timeout = Timeout; |
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403 |
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404 /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/ |
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405 while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0)) |
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406 { |
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407 timeout--; |
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408 } |
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409 |
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410 timeout = Timeout; |
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411 |
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412 while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0)) |
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413 { |
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414 timeout--; |
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415 } |
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416 |
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417 /*!< Get the NOR memory operation status -----------------------------------*/ |
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418 while((Timeout != 0x00) && (status != NOR_SUCCESS)) |
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419 { |
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420 Timeout--; |
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421 |
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422 /*!< Read DQ6 and DQ5 */ |
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423 val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); |
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424 val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); |
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425 |
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426 /*!< If DQ6 did not toggle between the two reads then return NOR_Success */ |
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427 if((val1 & 0x0040) == (val2 & 0x0040)) |
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428 { |
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429 return NOR_SUCCESS; |
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430 } |
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431 |
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432 if((val1 & 0x0020) != 0x0020) |
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433 { |
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434 status = NOR_ONGOING; |
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435 } |
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436 |
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437 val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); |
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438 val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR); |
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439 |
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440 if((val1 & 0x0040) == (val2 & 0x0040)) |
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441 { |
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442 return NOR_SUCCESS; |
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443 } |
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444 else if((val1 & 0x0020) == 0x0020) |
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445 { |
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446 return NOR_ERROR; |
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447 } |
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448 } |
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449 |
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450 if(Timeout == 0x00) |
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451 { |
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452 status = NOR_TIMEOUT; |
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453 } |
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454 |
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455 /*!< Return the operation status */ |
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456 return (status); |
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457 } |
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458 |
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459 /** |
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460 * @} |
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461 */ |
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462 |
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463 /** |
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464 * @} |
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465 */ |
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466 |
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467 /** |
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468 * @} |
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469 */ |
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470 |
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471 /** |
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472 * @} |
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473 */ |
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474 |
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475 /** |
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476 * @} |
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477 */ |
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478 |
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479 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |