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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c @ 48:2f336d212c74

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author Daniel O'Connor <darius@dons.net.au>
date Wed, 03 Apr 2013 23:33:47 +1030
parents c59513fd84fb
children
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1 /**
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2 ******************************************************************************
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3 * @file stm3210e_eval_fsmc_nand.c
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4 * @author MCD Application Team
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5 * @version V4.5.0
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6 * @date 07-March-2011
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7 * @brief This file provides a set of functions needed to drive the
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8 * NAND512W3A2 memory mounted on STM3210E-EVAL board.
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9 ******************************************************************************
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10 * @attention
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11 *
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *
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19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 ******************************************************************************
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21 */
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22
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23 /* Includes ------------------------------------------------------------------*/
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24 #include "stm3210e_eval_fsmc_nand.h"
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25
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26 /** @addtogroup Utilities
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27 * @{
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28 */
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29
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30 /** @addtogroup STM32_EVAL
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31 * @{
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32 */
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33
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34 /** @addtogroup STM3210E_EVAL
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35 * @{
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36 */
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37
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38 /** @addtogroup STM3210E_EVAL_FSMC_NAND
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39 * @brief This file provides a set of functions needed to drive the
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40 * NAND512W3A2 memory mounted on STM3210E-EVAL board.
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41 * @{
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42 */
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43
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44 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types
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45 * @{
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46 */
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47 /**
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48 * @}
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49 */
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50
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51
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52 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines
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53 * @{
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54 */
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55 /**
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56 * @brief FSMC Bank 2
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57 */
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58 #define FSMC_Bank_NAND FSMC_Bank2_NAND
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59 #define Bank_NAND_ADDR Bank2_NAND_ADDR
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60 #define Bank2_NAND_ADDR ((uint32_t)0x70000000)
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61 /**
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62 * @}
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63 */
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64
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65 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros
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66 * @{
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67 */
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68 #define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
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69 /**
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70 * @}
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71 */
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72
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73
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74 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables
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75 * @{
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76 */
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77 /**
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78 * @}
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79 */
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80
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81
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82 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
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83 * @{
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84 */
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85 /**
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86 * @}
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87 */
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88
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89
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90 /** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions
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91 * @{
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92 */
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93
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94 /**
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95 * @brief Configures the FSMC and GPIOs to interface with the NAND memory.
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96 * This function must be called before any write/read operation on the
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97 * NAND.
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98 * @param None
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99 * @retval None
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100 */
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101 void NAND_Init(void)
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102 {
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103 GPIO_InitTypeDef GPIO_InitStructure;
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104 FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
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105 FSMC_NAND_PCCARDTimingInitTypeDef p;
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106
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107 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
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108 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
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109
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110 /*-- GPIO Configuration ------------------------------------------------------*/
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111 /*!< CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
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112 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
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113 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
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114 GPIO_Pin_7;
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115 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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116 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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117
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118 GPIO_Init(GPIOD, &GPIO_InitStructure);
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119
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120 /*!< D4->D7 NAND pin configuration */
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121 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
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122
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123 GPIO_Init(GPIOE, &GPIO_InitStructure);
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124
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125
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126 /*!< NWAIT NAND pin configuration */
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127 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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128 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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129 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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130
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131 GPIO_Init(GPIOD, &GPIO_InitStructure);
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132
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133 /*!< INT2 NAND pin configuration */
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134 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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135 GPIO_Init(GPIOG, &GPIO_InitStructure);
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136
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137 /*-- FSMC Configuration ------------------------------------------------------*/
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138 p.FSMC_SetupTime = 0x0;
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139 p.FSMC_WaitSetupTime = 0x2;
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140 p.FSMC_HoldSetupTime = 0x1;
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141 p.FSMC_HiZSetupTime = 0x0;
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142
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143 FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
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144 FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
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145 FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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146 FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
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147 FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
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148 FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
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149 FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
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150 FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
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151 FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
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152
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153 FSMC_NANDInit(&FSMC_NANDInitStructure);
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154
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155 /*!< FSMC NAND Bank Cmd Test */
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156 FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
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157 }
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158
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159 /**
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160 * @brief Reads NAND memory's ID.
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161 * @param NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
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162 * the Manufacturer and Device ID.
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163 * @retval None
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164 */
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165 void NAND_ReadID(NAND_IDTypeDef* NAND_ID)
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166 {
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167 uint32_t data = 0;
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168
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169 /*!< Send Command to the command area */
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170 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
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171 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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172
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173 /*!< Sequence to read ID from NAND flash */
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174 data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
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175
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176 NAND_ID->Maker_ID = ADDR_1st_CYCLE (data);
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177 NAND_ID->Device_ID = ADDR_2nd_CYCLE (data);
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178 NAND_ID->Third_ID = ADDR_3rd_CYCLE (data);
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179 NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data);
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180 }
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181
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182 /**
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183 * @brief This routine is for writing one or several 512 Bytes Page size.
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184 * @param pBuffer: pointer on the Buffer containing data to be written
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185 * @param Address: First page address
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186 * @param NumPageToWrite: Number of page to write
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187 * @retval New status of the NAND operation. This parameter can be:
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188 * - NAND_TIMEOUT_ERROR: when the previous operation generate
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189 * a Timeout error
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190 * - NAND_READY: when memory is ready for the next operation
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191 * And the new status of the increment address operation. It can be:
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192 * - NAND_VALID_ADDRESS: When the new address is valid address
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193 * - NAND_INVALID_ADDRESS: When the new address is invalid address
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194 */
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195 uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
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196 {
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197 uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
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198 uint32_t status = NAND_READY, size = 0x00;
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199
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200 while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
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201 {
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202 /*!< Page write command and address */
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203 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
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204 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
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205
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206 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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207 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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208 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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209 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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210
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211 /*!< Calculate the size */
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212 size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
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213
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214 /*!< Write data */
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215 for(; index < size; index++)
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216 {
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217 *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
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218 }
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219
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220 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
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221
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222 /*!< Check status for successful operation */
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223 status = NAND_GetStatus();
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224
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225 if(status == NAND_READY)
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226 {
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227 numpagewritten++;
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228
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229 NumPageToWrite--;
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230
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231 /*!< Calculate Next small page Address */
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232 addressstatus = NAND_AddressIncrement(&Address);
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233 }
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234 }
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235
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236 return (status | addressstatus);
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237 }
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238
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239 /**
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240 * @brief This routine is for sequential read from one or several 512 Bytes Page size.
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241 * @param pBuffer: pointer on the Buffer to fill
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242 * @param Address: First page address
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243 * @param NumPageToRead: Number of page to read
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244 * @retval New status of the NAND operation. This parameter can be:
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245 * - NAND_TIMEOUT_ERROR: when the previous operation generate
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246 * a Timeout error
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247 * - NAND_READY: when memory is ready for the next operation
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248 * And the new status of the increment address operation. It can be:
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249 * - NAND_VALID_ADDRESS: When the new address is valid address
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250 * - NAND_INVALID_ADDRESS: When the new address is invalid address
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251 */
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252 uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
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253 {
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254 uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
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255 uint32_t status = NAND_READY, size = 0x00;
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256
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257 while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
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258 {
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259 /*!< Page Read command and page address */
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260 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
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261
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262 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
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263 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
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264 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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265 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
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266
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267 /*!< Calculate the size */
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268 size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
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269
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270 /*!< Get Data into Buffer */
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271 for(; index < size; index++)
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272 {
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273 pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
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274 }
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275
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276 numpageread++;
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277
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278 NumPageToRead--;
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279
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280 /*!< Calculate page address */
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281 addressstatus = NAND_AddressIncrement(&Address);
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282 }
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283
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284 status = NAND_GetStatus();
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285
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286 return (status | addressstatus);
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287 }
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288
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289 /**
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290 * @brief This routine write the spare area information for the specified
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291 * pages addresses.
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292 * @param pBuffer: pointer on the Buffer containing data to be written
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293 * @param Address: First page address
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diff changeset
294 * @param NumSpareAreaTowrite: Number of Spare Area to write
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parents:
diff changeset
295 * @retval New status of the NAND operation. This parameter can be:
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
296 * - NAND_TIMEOUT_ERROR: when the previous operation generate
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
297 * a Timeout error
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
298 * - NAND_READY: when memory is ready for the next operation
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
299 * And the new status of the increment address operation. It can be:
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
300 * - NAND_VALID_ADDRESS: When the new address is valid address
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
301 * - NAND_INVALID_ADDRESS: When the new address is invalid address
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
302 */
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diff changeset
303 uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
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parents:
diff changeset
304 {
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
305 uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
306 uint32_t status = NAND_READY, size = 0x00;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
307
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
308 while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
309 {
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
310 /*!< Page write Spare area command and address */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
311 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
312 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
313
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
314 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
315 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
316 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
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parents:
diff changeset
317 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
318
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
319 /*!< Calculate the size */
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diff changeset
320 size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
321
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
322 /*!< Write the data */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
323 for(; index < size; index++)
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parents:
diff changeset
324 {
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
325 *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
326 }
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
327
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
328 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
329
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
330 /*!< Check status for successful operation */
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diff changeset
331 status = NAND_GetStatus();
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parents:
diff changeset
332
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
333 if(status == NAND_READY)
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
334 {
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
335 numsparesreawritten++;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
336
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
337 NumSpareAreaTowrite--;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
338
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
339 /*!< Calculate Next page Address */
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diff changeset
340 addressstatus = NAND_AddressIncrement(&Address);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
341 }
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
342 }
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
343
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
344 return (status | addressstatus);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
345 }
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
346
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
347 /**
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
348 * @brief This routine read the spare area information from the specified
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
349 * pages addresses.
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
350 * @param pBuffer: pointer on the Buffer to fill
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
351 * @param Address: First page address
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
352 * @param NumSpareAreaToRead: Number of Spare Area to read
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
353 * @retval New status of the NAND operation. This parameter can be:
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
354 * - NAND_TIMEOUT_ERROR: when the previous operation generate
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
355 * a Timeout error
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
356 * - NAND_READY: when memory is ready for the next operation
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
357 * And the new status of the increment address operation. It can be:
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
358 * - NAND_VALID_ADDRESS: When the new address is valid address
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
359 * - NAND_INVALID_ADDRESS: When the new address is invalid address
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
360 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
361 uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
362 {
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
363 uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
364 uint32_t status = NAND_READY, size = 0x00;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
365
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
366 while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
367 {
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
368 /*!< Page Read command and page address */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
369 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
370
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
371 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
372 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
373 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
374 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
375
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
376 /*!< Data Read */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
377 size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
378
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
379 /*!< Get Data into Buffer */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
380 for ( ;index < size; index++)
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
381 {
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
382 pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
383 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
384
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
385 numsparearearead++;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
386
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
387 NumSpareAreaToRead--;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
388
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
389 /*!< Calculate page address */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
390 addressstatus = NAND_AddressIncrement(&Address);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
391 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
392
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
393 status = NAND_GetStatus();
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
394
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
395 return (status | addressstatus);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
396 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
397
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
398 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
399 * @brief This routine erase complete block from NAND FLASH
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
400 * @param Address: Any address into block to be erased
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
401 * @retval New status of the NAND operation. This parameter can be:
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
402 * - NAND_TIMEOUT_ERROR: when the previous operation generate
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
403 * a Timeout error
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
404 * - NAND_READY: when memory is ready for the next operation
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
405 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
406 uint32_t NAND_EraseBlock(NAND_ADDRESS Address)
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
407 {
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
408 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
409
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
410 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
411 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
412 *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
413
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
414 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
415
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
416 return (NAND_GetStatus());
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
417 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
418
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
419 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
420 * @brief This routine reset the NAND FLASH.
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
421 * @param None
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
422 * @retval NAND_READY
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
423 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
424 uint32_t NAND_Reset(void)
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
425 {
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
426 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
427
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
428 return (NAND_READY);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
429 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
430
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
431 /**
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
432 * @brief Get the NAND operation status.
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
433 * @param None
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
434 * @retval New status of the NAND operation. This parameter can be:
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
435 * - NAND_TIMEOUT_ERROR: when the previous operation generate
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
436 * a Timeout error
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
437 * - NAND_READY: when memory is ready for the next operation
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
438 */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
439 uint32_t NAND_GetStatus(void)
c59513fd84fb Initial commit of STM32 test code.
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440 {
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441 uint32_t timeout = 0x1000000, status = NAND_READY;
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442
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443 status = NAND_ReadStatus();
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444
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445 /*!< Wait for a NAND operation to complete or a TIMEOUT to occur */
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446 while ((status != NAND_READY) &&( timeout != 0x00))
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447 {
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448 status = NAND_ReadStatus();
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449 timeout --;
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450 }
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451
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452 if(timeout == 0x00)
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453 {
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454 status = NAND_TIMEOUT_ERROR;
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455 }
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456
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457 /*!< Return the operation status */
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458 return (status);
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459 }
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460
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461 /**
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462 * @brief Reads the NAND memory status using the Read status command.
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463 * @param None
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464 * @retval The status of the NAND memory. This parameter can be:
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465 * - NAND_BUSY: when memory is busy
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466 * - NAND_READY: when memory is ready for the next operation
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467 * - NAND_ERROR: when the previous operation gererates error
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468 */
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469 uint32_t NAND_ReadStatus(void)
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470 {
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471 uint32_t data = 0x00, status = NAND_BUSY;
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472
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473 /*!< Read status operation ------------------------------------ */
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474 *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
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475 data = *(__IO uint8_t *)(Bank_NAND_ADDR);
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476
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477 if((data & NAND_ERROR) == NAND_ERROR)
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478 {
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479 status = NAND_ERROR;
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480 }
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481 else if((data & NAND_READY) == NAND_READY)
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482 {
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483 status = NAND_READY;
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484 }
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485 else
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486 {
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487 status = NAND_BUSY;
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488 }
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489
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490 return (status);
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491 }
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492
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493 /**
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494 * @brief Increment the NAND memory address.
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495 * @param Address: address to be incremented.
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496 * @retval The new status of the increment address operation. It can be:
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497 * - NAND_VALID_ADDRESS: When the new address is valid address
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498 * - NAND_INVALID_ADDRESS: When the new address is invalid address
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499 */
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500 uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address)
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501 {
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502 uint32_t status = NAND_VALID_ADDRESS;
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503
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504 Address->Page++;
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505
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506 if(Address->Page == NAND_BLOCK_SIZE)
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507 {
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508 Address->Page = 0;
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509 Address->Block++;
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510
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511 if(Address->Block == NAND_ZONE_SIZE)
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512 {
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513 Address->Block = 0;
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514 Address->Zone++;
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515
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516 if(Address->Zone == NAND_MAX_ZONE)
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517 {
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518 status = NAND_INVALID_ADDRESS;
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519 }
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520 }
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521 }
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522
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523 return (status);
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524 }
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525
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526 /**
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527 * @}
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528 */
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529
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Daniel O'Connor <darius@dons.net.au>
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530 /**
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531 * @}
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532 */
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533
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Daniel O'Connor <darius@dons.net.au>
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534 /**
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535 * @}
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536 */
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537
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538 /**
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539 * @}
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540 */
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541
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542 /**
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543 * @}
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544 */
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545
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546 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/