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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.c @ 48:2f336d212c74

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author Daniel O'Connor <darius@dons.net.au>
date Wed, 03 Apr 2013 23:33:47 +1030
parents c59513fd84fb
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32100e_eval_fsmc_sram.c
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4 * @author MCD Application Team
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5 * @version V4.5.0
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6 * @date 07-March-2011
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7 * @brief This file provides a set of functions needed to drive the
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8 * IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.
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9 ******************************************************************************
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10 * @attention
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11 *
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *
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19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 ******************************************************************************
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21 */
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22
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23 /* Includes ------------------------------------------------------------------*/
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24 #include "stm32100e_eval_fsmc_sram.h"
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25
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26 /** @addtogroup Utilities
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27 * @{
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28 */
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29
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30 /** @addtogroup STM32_EVAL
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31 * @{
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32 */
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33
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34 /** @addtogroup STM32100E_EVAL
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35 * @{
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36 */
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37
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38 /** @addtogroup STM32100E_EVAL_FSMC_SRAM
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39 * @brief This file provides a set of functions needed to drive the
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40 * IS61WV102416BLL SRAM memory mounted on STM32100E-EVAL board.
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41 * @{
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42 */
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43
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44 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Types
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45 * @{
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46 */
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47 /**
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48 * @}
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49 */
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50
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51
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52 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Defines
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53 * @{
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54 */
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55 /**
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56 * @brief FSMC Bank 1 NOR/SRAM3
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57 */
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58 #define Bank1_SRAM3_ADDR ((uint32_t)0x68000000)
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59 /**
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60 * @}
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61 */
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62
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63
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64 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Macros
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65 * @{
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66 */
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67 /**
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68 * @}
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69 */
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70
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71
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72 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Variables
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73 * @{
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74 */
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75 /**
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76 * @}
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77 */
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78
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79
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80 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Function_Prototypes
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81 * @{
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82 */
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83 /**
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84 * @}
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85 */
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86
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87
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88 /** @defgroup STM32100E_EVAL_FSMC_SRAM_Private_Functions
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89 * @{
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90 */
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91
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92 /**
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93 * @brief Configures the FSMC and GPIOs to interface with the SRAM memory.
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94 * This function must be called before any write/read operation
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95 * on the SRAM.
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96 * @param None
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97 * @retval None
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98 */
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99 void SRAM_Init(void)
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100 {
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101 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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102 FSMC_NORSRAMTimingInitTypeDef p;
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103 GPIO_InitTypeDef GPIO_InitStructure;
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104
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105 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
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106 RCC_APB2Periph_GPIOF, ENABLE);
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107
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108 /*-- GPIO Configuration ------------------------------------------------------*/
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109 /*!< SRAM Data lines configuration */
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110 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
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111 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
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112 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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113 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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114 GPIO_Init(GPIOD, &GPIO_InitStructure);
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115
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116 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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117 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
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118 GPIO_Pin_15;
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119 GPIO_Init(GPIOE, &GPIO_InitStructure);
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120
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121 /*!< SRAM Address lines configuration */
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122 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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123 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
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124 GPIO_Pin_14 | GPIO_Pin_15;
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125 GPIO_Init(GPIOF, &GPIO_InitStructure);
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126
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127 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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128 GPIO_Pin_4 | GPIO_Pin_5;
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129 GPIO_Init(GPIOG, &GPIO_InitStructure);
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130
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131 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
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132 GPIO_Init(GPIOD, &GPIO_InitStructure);
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133
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134 /*!< NOE and NWE configuration */
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135 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
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136 GPIO_Init(GPIOD, &GPIO_InitStructure);
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137
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138 /*!< NE3 configuration */
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139 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
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140 GPIO_Init(GPIOG, &GPIO_InitStructure);
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141
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142 /*!< NBL0, NBL1 configuration */
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143 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
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144 GPIO_Init(GPIOE, &GPIO_InitStructure);
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145
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146 /*-- FSMC Configuration ------------------------------------------------------*/
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147 p.FSMC_AddressSetupTime = 0;
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148 p.FSMC_AddressHoldTime = 0;
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149 p.FSMC_DataSetupTime = 3;
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150 p.FSMC_BusTurnAroundDuration = 0;
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151 p.FSMC_CLKDivision = 0;
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152 p.FSMC_DataLatency = 0;
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153 p.FSMC_AccessMode = FSMC_AccessMode_A;
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154
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155 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
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156 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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157 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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158 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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159 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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160 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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161 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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162 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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163 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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164 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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165 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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166 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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167 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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168 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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169 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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170
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171 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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172
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173 /*!< Enable FSMC Bank1_SRAM Bank */
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174 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
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175 }
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176
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177 /**
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178 * @brief Writes a Half-word buffer to the FSMC SRAM memory.
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179 * @param pBuffer : pointer to buffer.
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180 * @param WriteAddr : SRAM memory internal address from which the data will be
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181 * written.
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182 * @param NumHalfwordToWrite : number of half-words to write.
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183 * @retval None
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184 */
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185 void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
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186 {
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187 for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
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188 {
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189 /*!< Transfer data to the memory */
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190 *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
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191
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192 /*!< Increment the address*/
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193 WriteAddr += 2;
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194 }
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195 }
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196
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197 /**
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198 * @brief Reads a block of data from the FSMC SRAM memory.
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199 * @param pBuffer : pointer to the buffer that receives the data read from the
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200 * SRAM memory.
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201 * @param ReadAddr : SRAM memory internal address to read from.
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202 * @param NumHalfwordToRead : number of half-words to read.
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203 * @retval None
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204 */
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205 void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
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206 {
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207 for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
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208 {
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209 /*!< Read a half-word from the memory */
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210 *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
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211
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212 /*!< Increment the address*/
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213 ReadAddr += 2;
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214 }
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215 }
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216
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217 /**
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218 * @}
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219 */
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220
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221 /**
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222 * @}
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223 */
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224
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225 /**
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226 * @}
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227 */
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228
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229 /**
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230 * @}
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231 */
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232
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233 /**
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234 * @}
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235 */
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236
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237 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/