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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c @ 48:2f336d212c74

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author Daniel O'Connor <darius@dons.net.au>
date Wed, 03 Apr 2013 23:33:47 +1030
parents c59513fd84fb
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32100e_eval_fsmc_onenand.c
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4 * @author MCD Application Team
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5 * @version V4.5.0
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6 * @date 07-March-2011
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7 * @brief This file provides a set of functions needed to drive the
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8 * KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.
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9 ******************************************************************************
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10 * @attention
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11 *
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *
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19 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 ******************************************************************************
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21 */
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22
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23 /* Includes ------------------------------------------------------------------*/
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24 #include "stm32100e_eval_fsmc_onenand.h"
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25
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26 /** @addtogroup Utilities
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27 * @{
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28 */
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29
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30 /** @addtogroup STM32_EVAL
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31 * @{
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32 */
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33
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34 /** @addtogroup STM32100E_EVAL
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35 * @{
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36 */
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37
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38 /** @addtogroup STM32100E_EVAL_FSMC_ONENAND
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39 * @brief This file provides a set of functions needed to drive the
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40 * KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
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41 * @{
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42 */
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43
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44 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
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45 * @{
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46 */
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47 /**
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48 * @}
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49 */
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50
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51
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52 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
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53 * @{
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54 */
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55 #define BANK1_ONENAND1_ADDR ((uint32_t)0x60000000)
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56 #define ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR)
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57
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58
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59 /**
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60 * @}
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61 */
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62
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63 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
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64 * @{
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65 */
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66 #define OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data))
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67
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68 /**
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69 * @}
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70 */
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71
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72
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73 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
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74 * @{
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75 */
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76 /**
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77 * @}
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78 */
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79
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80
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81 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
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82 * @{
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83 */
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84 /**
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85 * @}
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86 */
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87
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88
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89 /** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
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90 * @{
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91 */
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92
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93 /**
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94 * @brief Configures the FSMC and GPIOs to interface with the OneNAND memory.
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95 * This function must be called before any write/read operation on the
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96 * OneNAND.
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97 * @param None
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98 * @retval None
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99 */
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100 void OneNAND_Init(void)
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101 {
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102 FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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103 FSMC_NORSRAMTimingInitTypeDef p;
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104 GPIO_InitTypeDef GPIO_InitStructure;
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105
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106
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107 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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108
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109 /*-- GPIO Configuration ------------------------------------------------------*/
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110 /* OneNAND Data lines configuration */
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111 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
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112 RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
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113
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114 /*-- GPIO Configuration ------------------------------------------------------*/
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115 /*!< OneNAND Data lines configuration */
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116 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
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117 GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
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118 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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119 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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120 GPIO_Init(GPIOD, &GPIO_InitStructure);
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121
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122 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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123 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
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124 GPIO_Pin_15;
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125 GPIO_Init(GPIOE, &GPIO_InitStructure);
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126
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127 /*!< OneNAND Address lines configuration */
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128 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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129 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
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130 GPIO_Pin_14 | GPIO_Pin_15;
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131 GPIO_Init(GPIOF, &GPIO_InitStructure);
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132
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133 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
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134 GPIO_Pin_4 | GPIO_Pin_5;
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135 GPIO_Init(GPIOG, &GPIO_InitStructure);
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136
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137 /*!< CLK, NOE and NWE configuration */
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138 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
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139 GPIO_Init(GPIOD, &GPIO_InitStructure);
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140
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141 /*!< NE1 configuration */
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142 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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143 GPIO_Init(GPIOD, &GPIO_InitStructure);
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144
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145 /*!< NL configuration */
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146 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
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147 GPIO_Init(GPIOB, &GPIO_InitStructure);
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148 GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE);
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149
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150 /*!< NWAIT configuration */
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151 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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152 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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153 GPIO_Init(GPIOD, &GPIO_InitStructure);
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154
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155 /*-- FSMC Configuration ----------------------------------------------------*/
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156 p.FSMC_AddressSetupTime = 0x01;
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157 p.FSMC_AddressHoldTime = 0x00;
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158 p.FSMC_DataSetupTime = 0x05;
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159 p.FSMC_BusTurnAroundDuration = 0x02;
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160 p.FSMC_CLKDivision = 0x1;
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161 p.FSMC_DataLatency = 0x01;
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162 p.FSMC_AccessMode = FSMC_AccessMode_B;
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163
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164 FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
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165 FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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166 FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
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167 FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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168 FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
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169 FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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170 FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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171 FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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172 FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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173 FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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174 FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable;
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175 FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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176 FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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177 FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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178 FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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179
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180 FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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181 FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
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182 }
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183
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184 /**
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185 * @brief Resets the OneNAND memory.
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186 * @param None
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187 * @retval None
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188 */
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189 void OneNAND_Reset(void)
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190 {
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191 OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET);
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192 }
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193
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194 /**
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195 * @brief Reads OneNAND memory's Manufacturer and Device Code.
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196 * @param OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
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197 * the Manufacturer and Device Code.
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198 * @retval None
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199 */
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200 void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
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201 {
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202 uint16_t status = 0x0;
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203
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204 /* Wait till no ongoing operation */
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205 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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206
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207 while((status & 0x8000) == 0x8000)
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208 {
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209 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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210 }
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211
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212 /* Read ID data */
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213 OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID);
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214 OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID);
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215
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216 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0;
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217 }
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218
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219 /**
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220 * @brief Unlocks the specified OneNAND memory block (128Kb).
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221 * @param BlockNumber: specifies the block number to be erased. This parameter
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222 * should be between 0 and 511.
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223 * @retval OneNAND memory Interrupt Status.
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224 */
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225 uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber)
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226 {
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227 uint16_t status = 0;
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228
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229 /* Wait till no ongoing operation */
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230 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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231
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diff changeset
232 while((status & 0x8000) == 0x8000)
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233 {
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234 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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235 }
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236
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237 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber;
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238 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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239 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK;
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240
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diff changeset
241 /* Wait till the command is completed */
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diff changeset
242 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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243
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diff changeset
244 while((status & 0x8000) != 0x8000)
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diff changeset
245 {
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246 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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247 }
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248
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249 /* Get the Controller Status */
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250 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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251
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252 return (status);
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diff changeset
253 }
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254
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diff changeset
255 /**
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diff changeset
256 * @brief Erases the specified OneNAND memory block (128Kb).
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diff changeset
257 * @param BlockNumber: specifies the block number to be erased. This parameter
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258 * should be between 0 and 511.
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259 * @retval OneNAND memory Interrupt Status.
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diff changeset
260 */
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diff changeset
261 uint16_t OneNAND_EraseBlock(uint32_t BlockNumber)
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diff changeset
262 {
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263 uint16_t status = 0x0;
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264
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diff changeset
265 /* Wait till no ongoing operation */
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266 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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267
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268 while((status & 0x8000) == 0x8000)
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diff changeset
269 {
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270 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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271 }
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272
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273 /* Erase operation */
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274 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber;
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275 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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276 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE;
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277
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diff changeset
278 /* Wait till no error is generated */
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279 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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280
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281 while((status & 0x0400) == 0x0400)
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diff changeset
282 {
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283 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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284 }
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285
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diff changeset
286 /* Wait till the command is completed */
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287 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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288
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289 while((status & 0x8000) != 0x8000)
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290 {
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291 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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292 }
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293
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294 /* Get the Controller Status */
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295 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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296
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diff changeset
297 return (status);
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diff changeset
298 }
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299
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parents:
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300 /**
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diff changeset
301 * @brief Writes a Half-word buffer to the OneNAND memory.
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302 * @param pBuffer: pointer to buffer.
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303 * @param WriteAddr: OneNAND memory internal address from which the data will be
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diff changeset
304 * written.
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305 * @param NumHalfwordToWrite: number of half-words to write.
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306 * @retval OneNAND memory Controller Status.
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307 */
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308 uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
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309 {
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310 uint32_t datacounter = 0;
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311 uint16_t status = 0;
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312
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diff changeset
313 /* Load the buffer to be written into the DATA RAM0*/
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diff changeset
314 for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
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315 {
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316 *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter];
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317 }
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318
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319 /* Write operation from DATA RAM0 to NAND address*/
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320 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
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321 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); /* NAND Flash start page address */
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322 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/
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323 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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324 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */
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325
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diff changeset
326 /* Wait till the command is completed */
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327 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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diff changeset
328
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diff changeset
329 while((status & 0x8000) != 0x8000)
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diff changeset
330 {
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331 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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332 }
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parents:
diff changeset
333
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
334 /* Wait till the write interrupt is set */
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335 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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diff changeset
336
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
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diff changeset
337 while((status & 0x40) != 0x40)
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diff changeset
338 {
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339 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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340 }
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diff changeset
341
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diff changeset
342 /* Get the Controller Status */
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343 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
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344
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diff changeset
345 return (status);
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diff changeset
346 }
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diff changeset
347
c59513fd84fb Initial commit of STM32 test code.
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348 /**
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349 * @brief Reads a block of data from the OneNAND memory using asynchronous mode.
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350 * @param pBuffer: pointer to the buffer that receives the data read from the
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351 * OneNAND memory.
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diff changeset
352 * @param ReadAddr: OneNAND memory internal address to read from.
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diff changeset
353 * @param NumHalfwordToRead: number of half-words to read.
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354 * @retval None
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355 */
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356 void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
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357 {
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diff changeset
358 uint16_t datatmp = 0x0, index = 0;
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diff changeset
359 uint16_t status = 0;
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diff changeset
360
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361 datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION);
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diff changeset
362
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diff changeset
363 /* Set the asynchronous read mode */
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diff changeset
364 OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF));
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
365
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
366 /* Load data from the read address to the DATA RAM 1 setor 1 */
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diff changeset
367 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
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diff changeset
368 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
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369 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
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diff changeset
370 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
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diff changeset
371 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
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parents:
diff changeset
372
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
373 /* Wait till the command is completed */
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diff changeset
374 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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diff changeset
375
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
376 while((status & 0x8000) != 0x8000)
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parents:
diff changeset
377 {
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diff changeset
378 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
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diff changeset
379 }
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
380
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diff changeset
381 /* Read Controller status */
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diff changeset
382 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
383
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
384 /* Read data */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
385 for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
386 {
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
387 /* Read a Halfword from the memory */
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diff changeset
388 *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index);
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
389 index++;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
390 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
391 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
392
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
393 /**
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
394 * @brief Reads a block of data from the OneNAND memory using synchronous mode.
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
395 * @param pBuffer: pointer to the buffer that receives the data read from the
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
396 * OneNAND memory.
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
397 * @param ReadAddr: OneNAND memory internal address to read from.
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
398 * @param NumHalfwordToRead: number of half-words to read.
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
399 * @retval None
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
400 */
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diff changeset
401 void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
402 {
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diff changeset
403 uint16_t index = 0;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
404 uint16_t status = 0;
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
405
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
406 /* Set the asynchronous read mode */
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
407 OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
408
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
409
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
410 /* Load data from the read address to the DATA RAM 1 setor 1 */
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
411 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
412 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
413 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
414 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
c59513fd84fb Initial commit of STM32 test code.
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parents:
diff changeset
415 *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
416
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
417 /* Wait till the command is completed */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
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diff changeset
418 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
419
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
420 while((status & 0x8000) != 0x8000)
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
421 {
c59513fd84fb Initial commit of STM32 test code.
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diff changeset
422 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
423 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
424
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
425 /* Read Controller status */
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
426 status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
427
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428 /* Read data */
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429 for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
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430 {
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431 *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index));
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432 index++;
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433 }
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434 }
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435
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436 /**
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437 * @brief Reads the OneNAND memory Interrupt status.
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438 * @param None
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439 * @retval OneNAND memory Interrupt Status.
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440 */
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441 uint16_t OneNAND_ReadStatus(void)
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442 {
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443 __IO uint16_t status = 0x0;
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444
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445 /* Read Status */
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446 return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT));
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447 }
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448
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449 /**
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450 * @brief Reads the OneNAND Controller status.
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451 * @param None
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452 * @retval OneNAND Controller Status.
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453 */
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454 uint16_t OneNAND_ReadControllerStatus(void)
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455 {
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456 __IO uint16_t status = 0x0;
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457
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458 /* Read Controller Status */
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459 return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS));
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460 }
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461
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462 /**
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463 * @}
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464 */
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465
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466 /**
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467 * @}
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468 */
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469
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470 /**
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471 * @}
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472 */
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473
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474 /**
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475 * @}
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476 */
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477
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478 /**
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479 * @}
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480 */
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481
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482 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/