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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c @ 48:2f336d212c74
Ignore more emacs crap.
author | Daniel O'Connor <darius@dons.net.au> |
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date | Wed, 03 Apr 2013 23:33:47 +1030 |
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1 /** |
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2 ****************************************************************************** |
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3 * @file RCC/RCC_ClockConfig/main.c |
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4 * @author MCD Application Team |
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5 * @version V3.5.0 |
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6 * @date 08-April-2011 |
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7 * @brief Main program body. |
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8 ****************************************************************************** |
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9 * @attention |
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10 * |
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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17 * |
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18 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
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19 ****************************************************************************** |
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20 */ |
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21 |
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22 /* Includes ------------------------------------------------------------------*/ |
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23 #include "main.h" |
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24 |
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25 /** @addtogroup STM32F10x_StdPeriph_Examples |
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26 * @{ |
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27 */ |
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28 |
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29 |
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30 /** @addtogroup RCC_ClockConfig |
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31 * @{ |
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32 */ |
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33 |
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34 /* Private typedef -----------------------------------------------------------*/ |
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35 /* Private define ------------------------------------------------------------*/ |
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36 #define DELAY_COUNT 0x3FFFF |
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37 |
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38 /* Private macro -------------------------------------------------------------*/ |
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39 /* Private variables ---------------------------------------------------------*/ |
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40 GPIO_InitTypeDef GPIO_InitStructure; |
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41 RCC_ClocksTypeDef RCC_ClockFreq; |
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42 ErrorStatus HSEStartUpStatus; |
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43 |
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44 /* Private function prototypes -----------------------------------------------*/ |
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45 void NVIC_Configuration(void); |
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46 void Delay(__IO uint32_t nCount); |
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47 |
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48 void SetSysClock(void); |
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49 #ifdef SYSCLK_HSE |
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50 void SetSysClockToHSE(void); |
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51 #elif defined SYSCLK_FREQ_24MHz |
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52 void SetSysClockTo24(void); |
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53 #elif defined SYSCLK_FREQ_36MHz |
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54 void SetSysClockTo36(void); |
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55 #elif defined SYSCLK_FREQ_48MHz |
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56 void SetSysClockTo48(void); |
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57 #elif defined SYSCLK_FREQ_56MHz |
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58 void SetSysClockTo56(void); |
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59 #elif defined SYSCLK_FREQ_72MHz |
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60 void SetSysClockTo72(void); |
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61 #endif |
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62 |
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63 /* Private functions ---------------------------------------------------------*/ |
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64 |
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65 /** |
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66 * @brief Main program. |
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67 * @param None |
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68 * @retval None |
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69 */ |
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70 int main(void) |
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71 { |
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72 /*!< At this stage the microcontroller clock setting is already configured, |
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73 this is done through SystemInit() function which is called from startup |
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74 file (startup_stm32f10x_xx.s) before to branch to application main. |
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75 To reconfigure the default setting of SystemInit() function, refer to |
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76 system_stm32f10x.c file |
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77 */ |
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78 |
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79 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ |
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80 SetSysClock(); |
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81 |
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82 /* This function fills the RCC_ClockFreq structure with the current |
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83 frequencies of different on chip clocks (for debug purpose) */ |
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84 RCC_GetClocksFreq(&RCC_ClockFreq); |
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85 |
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86 /* Enable Clock Security System(CSS): this will generate an NMI exception |
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87 when HSE clock fails */ |
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88 RCC_ClockSecuritySystemCmd(ENABLE); |
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89 |
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90 /* NVIC configuration ------------------------------------------------------*/ |
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91 NVIC_Configuration(); |
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92 |
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93 /* Initialize Leds mounted on STM3210X-EVAL board --------------------------*/ |
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94 STM_EVAL_LEDInit(LED1); |
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95 STM_EVAL_LEDInit(LED2); |
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96 STM_EVAL_LEDInit(LED3); |
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97 STM_EVAL_LEDInit(LED4); |
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98 |
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99 /* Output HSE clock on MCO pin ---------------------------------------------*/ |
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100 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); |
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101 |
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102 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; |
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103 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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104 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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105 GPIO_Init(GPIOA, &GPIO_InitStructure); |
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106 RCC_MCOConfig(RCC_MCO_HSE); |
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107 |
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108 while (1) |
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109 { |
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110 /* Toggle LED1 */ |
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111 STM_EVAL_LEDToggle(LED1); |
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112 /* Insert delay */ |
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113 Delay(DELAY_COUNT); |
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114 |
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115 /* Toggle LED2 */ |
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116 STM_EVAL_LEDToggle(LED2); |
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117 /* Insert delay */ |
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118 Delay(DELAY_COUNT); |
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119 |
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120 /* Toggle LED3 */ |
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121 STM_EVAL_LEDToggle(LED3); |
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122 /* Insert delay */ |
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123 Delay(DELAY_COUNT); |
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124 |
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125 /* Toggle LED4 */ |
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126 STM_EVAL_LEDToggle(LED4); |
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127 /* Insert a delay */ |
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128 Delay(DELAY_COUNT); |
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129 } |
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130 } |
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131 |
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132 /** |
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133 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 |
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134 * prescalers. |
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135 * @param None |
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136 * @retval None |
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137 */ |
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138 void SetSysClock(void) |
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139 { |
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140 /* The System clock configuration functions defined below assume that: |
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141 - For Low, Medium and High density devices an external 8MHz crystal is |
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142 used to drive the System clock. |
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143 - For Connectivity line devices an external 25MHz crystal is used to drive |
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144 the System clock. |
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145 If you are using different crystal you have to adapt those functions accordingly.*/ |
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146 |
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147 #if defined SYSCLK_HSE |
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148 SetSysClockToHSE(); |
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149 #elif defined SYSCLK_FREQ_24MHz |
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150 SetSysClockTo24(); |
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151 #elif defined SYSCLK_FREQ_36MHz |
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152 SetSysClockTo36(); |
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153 #elif defined SYSCLK_FREQ_48MHz |
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154 SetSysClockTo48(); |
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155 #elif defined SYSCLK_FREQ_56MHz |
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156 SetSysClockTo56(); |
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157 #elif defined SYSCLK_FREQ_72MHz |
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158 SetSysClockTo72(); |
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159 #endif |
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160 |
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161 /* If none of the define above is enabled, the HSI is used as System clock |
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162 source (default after reset) */ |
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163 } |
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164 |
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165 /** |
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166 * @brief Selects HSE as System clock source and configure HCLK, PCLK2 |
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167 * and PCLK1 prescalers. |
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168 * @param None |
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169 * @retval None |
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170 */ |
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171 void SetSysClockToHSE(void) |
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172 { |
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173 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ |
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174 /* RCC system reset(for debug purpose) */ |
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175 RCC_DeInit(); |
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176 |
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177 /* Enable HSE */ |
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178 RCC_HSEConfig(RCC_HSE_ON); |
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179 |
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180 /* Wait till HSE is ready */ |
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181 HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
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182 |
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183 if (HSEStartUpStatus == SUCCESS) |
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184 { |
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185 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL |
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186 /* Enable Prefetch Buffer */ |
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187 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
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188 |
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189 #ifndef STM32F10X_CL |
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190 /* Flash 0 wait state */ |
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191 FLASH_SetLatency(FLASH_Latency_0); |
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192 #else |
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193 if (HSE_Value <= 24000000) |
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194 { |
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195 /* Flash 0 wait state */ |
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196 FLASH_SetLatency(FLASH_Latency_0); |
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197 } |
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198 else |
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199 { |
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200 /* Flash 1 wait state */ |
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201 FLASH_SetLatency(FLASH_Latency_1); |
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202 } |
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203 |
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204 #endif /* STM32F10X_CL */ |
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205 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */ |
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206 |
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207 /* HCLK = SYSCLK */ |
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208 RCC_HCLKConfig(RCC_SYSCLK_Div1); |
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209 |
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210 /* PCLK2 = HCLK */ |
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211 RCC_PCLK2Config(RCC_HCLK_Div1); |
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212 |
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213 /* PCLK1 = HCLK */ |
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214 RCC_PCLK1Config(RCC_HCLK_Div1); |
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215 |
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216 /* Select HSE as system clock source */ |
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217 RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE); |
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218 |
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219 /* Wait till PLL is used as system clock source */ |
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220 while (RCC_GetSYSCLKSource() != 0x04) |
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221 { |
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222 } |
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223 } |
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224 else |
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225 { /* If HSE fails to start-up, the application will have wrong clock configuration. |
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226 User can add here some code to deal with this error */ |
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227 |
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228 /* Go to infinite loop */ |
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229 while (1) |
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230 { |
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231 } |
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232 } |
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233 } |
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234 |
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235 /** |
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236 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 |
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237 * and PCLK1 prescalers. |
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238 * @param None |
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239 * @retval None |
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240 */ |
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241 void SetSysClockTo24(void) |
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242 { |
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243 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ |
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244 /* RCC system reset(for debug purpose) */ |
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245 RCC_DeInit(); |
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246 |
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247 /* Enable HSE */ |
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248 RCC_HSEConfig(RCC_HSE_ON); |
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249 |
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250 /* Wait till HSE is ready */ |
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251 HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
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252 |
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253 if (HSEStartUpStatus == SUCCESS) |
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254 { |
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255 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL |
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256 /* Enable Prefetch Buffer */ |
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257 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
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258 |
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259 /* Flash 0 wait state */ |
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260 FLASH_SetLatency(FLASH_Latency_0); |
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261 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */ |
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262 |
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263 /* HCLK = SYSCLK */ |
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264 RCC_HCLKConfig(RCC_SYSCLK_Div1); |
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265 |
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266 /* PCLK2 = HCLK */ |
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267 RCC_PCLK2Config(RCC_HCLK_Div1); |
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268 |
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269 /* PCLK1 = HCLK */ |
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270 RCC_PCLK1Config(RCC_HCLK_Div1); |
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271 |
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272 #ifdef STM32F10X_CL |
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273 /* Configure PLLs *********************************************************/ |
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274 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
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275 RCC_PREDIV2Config(RCC_PREDIV2_Div5); |
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276 RCC_PLL2Config(RCC_PLL2Mul_8); |
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277 |
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278 /* Enable PLL2 */ |
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279 RCC_PLL2Cmd(ENABLE); |
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280 |
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281 /* Wait till PLL2 is ready */ |
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282 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) |
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283 {} |
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284 |
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285 /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */ |
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286 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10); |
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287 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6); |
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288 #elif defined STM32F10X_LD_VL || defined STM32F10X_MD_VL || defined STM32F10X_HD_VL |
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289 /* PLLCLK = (8MHz/2) * 6 = 24 MHz */ |
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290 RCC_PREDIV1Config(RCC_PREDIV1_Source_HSE, RCC_PREDIV1_Div2); |
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291 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6); |
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292 #else |
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293 /* PLLCLK = 8MHz * 3 = 24 MHz */ |
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294 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3); |
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295 #endif |
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296 |
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297 /* Enable PLL */ |
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298 RCC_PLLCmd(ENABLE); |
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299 |
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300 /* Wait till PLL is ready */ |
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301 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) |
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302 { |
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303 } |
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304 |
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305 /* Select PLL as system clock source */ |
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306 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); |
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307 |
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308 /* Wait till PLL is used as system clock source */ |
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309 while (RCC_GetSYSCLKSource() != 0x08) |
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310 { |
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311 } |
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312 } |
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313 else |
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314 { /* If HSE fails to start-up, the application will have wrong clock configuration. |
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315 User can add here some code to deal with this error */ |
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316 |
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317 /* Go to infinite loop */ |
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318 while (1) |
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319 { |
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320 } |
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321 } |
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322 } |
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323 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL |
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324 /** |
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325 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 |
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326 * and PCLK1 prescalers. |
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327 * @param None |
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328 * @retval None |
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329 */ |
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330 void SetSysClockTo36(void) |
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331 { |
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332 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ |
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333 /* RCC system reset(for debug purpose) */ |
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334 RCC_DeInit(); |
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335 |
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336 /* Enable HSE */ |
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337 RCC_HSEConfig(RCC_HSE_ON); |
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338 |
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339 /* Wait till HSE is ready */ |
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340 HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
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341 |
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342 if (HSEStartUpStatus == SUCCESS) |
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343 { |
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344 /* Enable Prefetch Buffer */ |
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345 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
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346 |
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347 /* Flash 1 wait state */ |
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348 FLASH_SetLatency(FLASH_Latency_1); |
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349 |
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350 /* HCLK = SYSCLK */ |
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351 RCC_HCLKConfig(RCC_SYSCLK_Div1); |
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352 |
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353 /* PCLK2 = HCLK */ |
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354 RCC_PCLK2Config(RCC_HCLK_Div1); |
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355 |
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356 /* PCLK1 = HCLK */ |
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357 RCC_PCLK1Config(RCC_HCLK_Div1); |
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358 |
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359 #ifdef STM32F10X_CL |
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360 /* Configure PLLs *********************************************************/ |
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361 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
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362 RCC_PREDIV2Config(RCC_PREDIV2_Div5); |
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363 RCC_PLL2Config(RCC_PLL2Mul_8); |
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364 |
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365 /* Enable PLL2 */ |
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366 RCC_PLL2Cmd(ENABLE); |
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367 |
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368 /* Wait till PLL2 is ready */ |
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369 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) |
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370 {} |
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371 |
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372 /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */ |
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373 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10); |
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374 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); |
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375 #else |
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376 /* PLLCLK = (8MHz / 2) * 9 = 36 MHz */ |
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377 RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9); |
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378 #endif |
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379 |
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380 /* Enable PLL */ |
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381 RCC_PLLCmd(ENABLE); |
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382 |
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383 /* Wait till PLL is ready */ |
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384 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) |
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385 { |
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386 } |
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387 |
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388 /* Select PLL as system clock source */ |
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389 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); |
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390 |
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391 /* Wait till PLL is used as system clock source */ |
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392 while (RCC_GetSYSCLKSource() != 0x08) |
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393 { |
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394 } |
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395 } |
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396 else |
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397 { /* If HSE fails to start-up, the application will have wrong clock configuration. |
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398 User can add here some code to deal with this error */ |
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|
399 |
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400 /* Go to infinite loop */ |
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|
401 while (1) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
402 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
403 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
404 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
405 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
406 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
407 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
408 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
409 * and PCLK1 prescalers. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
410 * @param None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
411 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
412 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
413 void SetSysClockTo48(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
414 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
415 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
416 /* RCC system reset(for debug purpose) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
417 RCC_DeInit(); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
418 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
419 /* Enable HSE */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
420 RCC_HSEConfig(RCC_HSE_ON); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
421 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
422 /* Wait till HSE is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
423 HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
424 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
425 if (HSEStartUpStatus == SUCCESS) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
426 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
427 /* Enable Prefetch Buffer */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
428 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
429 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
430 /* Flash 1 wait state */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
431 FLASH_SetLatency(FLASH_Latency_1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
432 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
433 /* HCLK = SYSCLK */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
434 RCC_HCLKConfig(RCC_SYSCLK_Div1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
435 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
436 /* PCLK2 = HCLK */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
437 RCC_PCLK2Config(RCC_HCLK_Div1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
438 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
439 /* PCLK1 = HCLK/2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
440 RCC_PCLK1Config(RCC_HCLK_Div2); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
441 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
442 #ifdef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
443 /* Configure PLLs *********************************************************/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
444 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
445 RCC_PREDIV2Config(RCC_PREDIV2_Div5); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
446 RCC_PLL2Config(RCC_PLL2Mul_8); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
447 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
448 /* Enable PLL2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
449 RCC_PLL2Cmd(ENABLE); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
450 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
451 /* Wait till PLL2 is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
452 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
453 {} |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
454 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
455 /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
456 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
457 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
458 #else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
459 /* PLLCLK = 8MHz * 6 = 48 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
460 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_6); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
461 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
462 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
463 /* Enable PLL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
464 RCC_PLLCmd(ENABLE); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
465 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
466 /* Wait till PLL is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
467 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
468 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
469 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
470 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
471 /* Select PLL as system clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
472 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
473 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
474 /* Wait till PLL is used as system clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
475 while (RCC_GetSYSCLKSource() != 0x08) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
476 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
477 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
478 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
479 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
480 { /* If HSE fails to start-up, the application will have wrong clock configuration. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
481 User can add here some code to deal with this error */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
482 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
483 /* Go to infinite loop */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
484 while (1) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
485 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
486 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
487 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
488 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
489 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
490 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
491 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
492 * and PCLK1 prescalers. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
493 * @param None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
494 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
495 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
496 void SetSysClockTo56(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
497 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
498 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
499 /* RCC system reset(for debug purpose) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
500 RCC_DeInit(); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
501 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
502 /* Enable HSE */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
503 RCC_HSEConfig(RCC_HSE_ON); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
504 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
505 /* Wait till HSE is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
506 HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
507 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
508 if (HSEStartUpStatus == SUCCESS) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
509 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
510 /* Enable Prefetch Buffer */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
511 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
512 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
513 /* Flash 2 wait state */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
514 FLASH_SetLatency(FLASH_Latency_2); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
515 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
516 /* HCLK = SYSCLK */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
517 RCC_HCLKConfig(RCC_SYSCLK_Div1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
518 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
519 /* PCLK2 = HCLK */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
520 RCC_PCLK2Config(RCC_HCLK_Div1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
521 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
522 /* PCLK1 = HCLK/2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
523 RCC_PCLK1Config(RCC_HCLK_Div2); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
524 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
525 #ifdef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
526 /* Configure PLLs *********************************************************/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
527 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
528 RCC_PREDIV2Config(RCC_PREDIV2_Div5); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
529 RCC_PLL2Config(RCC_PLL2Mul_8); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
530 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
531 /* Enable PLL2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
532 RCC_PLL2Cmd(ENABLE); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
533 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
534 /* Wait till PLL2 is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
535 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
536 {} |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
537 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
538 /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
539 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
540 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_7); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
541 #else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
542 /* PLLCLK = 8MHz * 7 = 56 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
543 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7); |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
544 #endif |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
545 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
546 /* Enable PLL */ |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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|
547 RCC_PLLCmd(ENABLE); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
548 |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
549 /* Wait till PLL is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
550 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
551 { |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
552 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
553 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
554 /* Select PLL as system clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
555 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
556 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
557 /* Wait till PLL is used as system clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
558 while (RCC_GetSYSCLKSource() != 0x08) |
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Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
559 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
560 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
561 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
562 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
563 { /* If HSE fails to start-up, the application will have wrong clock configuration. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
564 User can add here some code to deal with this error */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
565 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
566 /* Go to infinite loop */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
567 while (1) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
568 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
569 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
570 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
571 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
572 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
573 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
574 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
575 * and PCLK1 prescalers. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
576 * @param None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
577 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
578 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
579 void SetSysClockTo72(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
580 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
581 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
582 /* RCC system reset(for debug purpose) */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
583 RCC_DeInit(); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
584 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
585 /* Enable HSE */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
586 RCC_HSEConfig(RCC_HSE_ON); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
587 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
588 /* Wait till HSE is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
589 HSEStartUpStatus = RCC_WaitForHSEStartUp(); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
590 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
591 if (HSEStartUpStatus == SUCCESS) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
592 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
593 /* Enable Prefetch Buffer */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
594 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
595 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
596 /* Flash 2 wait state */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
597 FLASH_SetLatency(FLASH_Latency_2); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
598 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
599 /* HCLK = SYSCLK */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
600 RCC_HCLKConfig(RCC_SYSCLK_Div1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
601 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
602 /* PCLK2 = HCLK */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
603 RCC_PCLK2Config(RCC_HCLK_Div1); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
604 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
605 /* PCLK1 = HCLK/2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
606 RCC_PCLK1Config(RCC_HCLK_Div2); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
607 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
608 #ifdef STM32F10X_CL |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
609 /* Configure PLLs *********************************************************/ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
610 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
611 RCC_PREDIV2Config(RCC_PREDIV2_Div5); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
612 RCC_PLL2Config(RCC_PLL2Mul_8); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
613 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
614 /* Enable PLL2 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
615 RCC_PLL2Cmd(ENABLE); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
616 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
617 /* Wait till PLL2 is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
618 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
619 {} |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
620 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
621 /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
622 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
623 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
624 #else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
625 /* PLLCLK = 8MHz * 9 = 72 MHz */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
626 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
627 #endif |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
628 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
629 /* Enable PLL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
630 RCC_PLLCmd(ENABLE); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
631 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
632 /* Wait till PLL is ready */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
633 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
634 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
635 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
636 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
637 /* Select PLL as system clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
638 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
639 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
640 /* Wait till PLL is used as system clock source */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
641 while(RCC_GetSYSCLKSource() != 0x08) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
642 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
643 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
644 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
645 else |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
646 { /* If HSE fails to start-up, the application will have wrong clock configuration. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
647 User can add here some code to deal with this error */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
648 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
649 /* Go to infinite loop */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
650 while (1) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
651 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
652 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
653 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
654 } |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
655 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
656 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
657 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
658 /** |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
659 * @brief Configures Vector Table base location. |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
660 * @param None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
661 * @retval None |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
662 */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
663 void NVIC_Configuration(void) |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
664 { |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
665 NVIC_InitTypeDef NVIC_InitStructure; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
666 |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
667 /* Enable and configure RCC global IRQ channel */ |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
668 NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
669 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
670 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
changeset
|
671 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; |
c59513fd84fb
Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff
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672 NVIC_Init(&NVIC_InitStructure); |
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673 } |
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674 |
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675 /** |
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676 * @brief Inserts a delay time. |
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677 * @param nCount: specifies the delay time length. |
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678 * @retval None |
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679 */ |
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680 void Delay(__IO uint32_t nCount) |
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681 { |
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682 for(; nCount!= 0;nCount--); |
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683 } |
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684 |
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685 #ifdef USE_FULL_ASSERT |
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686 |
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687 /** |
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688 * @brief Reports the name of the source file and the source line number |
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689 * where the assert_param error has occurred. |
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690 * @param file: pointer to the source file name |
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691 * @param line: assert_param error line source number |
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692 * @retval None |
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693 */ |
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694 void assert_failed(uint8_t* file, uint32_t line) |
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695 { |
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696 /* User can add his own implementation to report the file name and line number, |
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697 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ |
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698 |
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699 /* Infinite loop */ |
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700 while (1) |
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701 { |
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702 } |
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703 } |
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704 |
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705 #endif |
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706 |
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707 /** |
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708 * @} |
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709 */ |
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710 |
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711 /** |
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712 * @} |
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713 */ |
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714 |
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715 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |