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author Daniel O'Connor <darius@dons.net.au>
date Wed, 03 Apr 2013 23:33:47 +1030
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1 /**
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2 @page DMA_I2C_RAM DMA I2C to RAM example
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3
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4 @verbatim
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5 ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
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6 * @file DMA/I2C_RAM/readme.txt
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7 * @author MCD Application Team
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8 * @version V3.5.0
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9 * @date 08-April-2011
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10 * @brief Description of the DMA I2C to RAM example.
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11 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 ******************************************************************************
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19 @endverbatim
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20
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21 @par Example Description
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22
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23 This example provides a description of how to use two DMA channels to transfer a
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24 data buffer from memory to I2C2 through I2C1.
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25
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26 I2C1 is set as the master transmitter and I2C2 as the slave receiver. DMA1 Channel5 is
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27 configured to store the data received from I2C2 into the Rx buffer (reception buffer).
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28 DMA1 Channel6 is configured to transfer data from the Tx buffer (transmission buffer)
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29 to the I2C1 DR register. After the generation of the Start condition and once the slave
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30 address has been acknowledged, DMA capability is enabled for both I2C1 and I2C2.
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31 As soon as the two I2C DMAEN bits are set in the I2C1_CR2 and I2C2_CR2 registers,
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32 the transmission of the Tx buffer is started by DMA1 Channel5 and at the same time the
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33 data received on I2C2 is stored in Rx buffer using DMA1 Channel6 .
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34 The transmitted and the received buffers are compared to check that all data have been
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35 correctly transferred.
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36
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37
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38 @par Directory contents
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39
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40 - DMA/I2C_RAM/stm32f10x_conf.h Library Configuration file
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41 - DMA/I2C_RAM/stm32f10x_it.c Interrupt handlers
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42 - DMA/I2C_RAM/stm32f10x_it.h Interrupt handlers header file
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43 - DMA/I2C_RAM/main.c Main program
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44 - DMA/I2C_RAM/system_stm32f10x.c STM32F10x system source file
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45
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46
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47 @par Hardware and Software environment
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48
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49 - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density,
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50 XL-Density, High-Density Value line, Medium-Density Value line, Low-Density
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51 and Low-Density Value line Devices.
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52
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53 - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
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54 and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can
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55 be easily tailored to any other supported device and development board.
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56 This example can't be tested with STMicroelectronics STM3210C-EVAL (STM32F10x
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57 Connectivity-Line) evaluation boards since the I2C2 pins (PB10 and PB11) are
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58 already used by Ethernet PHY module.
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59 This example can't be tested with STMicroelectronics STM32100B-EVAL (STM32F10x
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60 Medium-Density Value line) and STM32100E-EVAL (High-Density Value line)
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61 evaluation boards since the I2C1/I2C2 pins (PB6/PB10 and PB7/PB11) are already
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62 used by HDMI-CEC module.
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63
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64 - STM3210E-EVAL Set-up
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65 - Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
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66 - Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin (PB.11)
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67 - Check that a pull-up resistor is connected on one I2C SDA pin
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68 - Check that a pull-up resistor is connected on one I2C SCL pin
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69
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70 - STM3210B-EVAL Set-up
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71 - Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
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72 - Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin (PB.11)
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73 - Check that a pull-up resistor is connected on one I2C SDA pin
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74 - Check that a pull-up resistor is connected on one I2C SCL pin
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75
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76 @par How to use it ?
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77
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78 In order to make the program work, you must do the following :
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79 - Copy all source files from this example folder to the template folder under
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80 Project\STM32F10x_StdPeriph_Template
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81 - Open your preferred toolchain
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82 - Rebuild all files and load your image into target memory
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83 - Run the example
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84
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85 @note
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86 - Low-density Value line devices are STM32F100xx microcontrollers where the
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87 Flash memory density ranges between 16 and 32 Kbytes.
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88 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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89 microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
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90 - Medium-density Value line devices are STM32F100xx microcontrollers where
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91 the Flash memory density ranges between 64 and 128 Kbytes.
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92 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
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93 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
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94 - High-density Value line devices are STM32F100xx microcontrollers where
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95 the Flash memory density ranges between 256 and 512 Kbytes.
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96 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
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97 the Flash memory density ranges between 256 and 512 Kbytes.
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98 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
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99 the Flash memory density ranges between 512 and 1024 Kbytes.
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100 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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101
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102 * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
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103 */