annotate 1wire-config.h @ 24:1e2fa7396f98

Reduce prescaler to 2, the flash is capable of 25MHz reads (although the touch screen is limited to ~2.5MHz)
author Daniel O'Connor <darius@dons.net.au>
date Sat, 17 Nov 2012 12:17:58 +1030
parents b12881051261
children 38869c474104
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
13
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
1 /*
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
2 * Example configuration header for 1-wire bus code.
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
3 *
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
4 * This is the user servicable stuff - how to do delays and how to
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
5 * frob the IO pins.
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
6 *
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
7 * Copyright (c) 2009
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
8 * Daniel O'Connor <darius@dons.net.au>. All rights reserved.
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
9 *
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
10 * Redistribution and use in source and binary forms, with or without
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
11 * modification, are permitted provided that the following conditions
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
12 * are met:
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
13 * 1. Redistributions of source code must retain the above copyright
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
14 * notice, this list of conditions and the following disclaimer.
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
15 * 2. Redistributions in binary form must reproduce the above copyright
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
16 * notice, this list of conditions and the following disclaimer in the
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
17 * documentation and/or other materials provided with the distribution.
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
18 *
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
29 * SUCH DAMAGE.
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
30 */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
31
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
32 /*
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
33 * The configuration described here has the 1-wire IO on GPIOE3,
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
34 * with no pull down, nor VPP
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
35 */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
36
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
37 #include "stm32f10x.h" /* GPIO* */
15
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
38 #include "delay.h"
13
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
39
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
40 /* Fudge AVR stuff for ARM */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
41 #define PROGMEM
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
42 #define PSTR(x) x
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
43 #define pgm_read_byte(x) *(x)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
44
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
45 /* Init bus */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
46 #define OWBUSINIT()
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
47
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
48 /* Set the port up to allow reading from the 1 wire bus */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
49 #define OWSETREAD() do { \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
50 GPIO_InitTypeDef GPIO_InitStructure; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
51 \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
52 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
53 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
54 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
55 GPIO_Init(GPIOE, &GPIO_InitStructure); \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
56 } while (0)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
57
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
58
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
59 /* Read the 1-wire bus, non-inverting logic */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
60 #define OWREADBUS() (GPIO_ReadInputDataBit(GPIOE, GPIO_Pin_3) ? 1 : 0)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
61
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
62 /* Set the 1-wire bus to 0
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
63 */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
64 #define OWSETBUSLOW() do { \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
65 GPIO_InitTypeDef GPIO_InitStructure; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
66 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
67 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
68 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
69 GPIO_Init(GPIOE, &GPIO_InitStructure); \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
70 GPIO_ResetBits(GPIOE, GPIO_Pin_3); \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
71 } while (0)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
72
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
73 /* Set the 1-wire bus to 1
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
74 * Change to input and let the pull up do its job
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
75 */
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
76 #define OWSETBUSHIGH() do { \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
77 GPIO_InitTypeDef GPIO_InitStructure; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
78 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
79 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
80 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
81 GPIO_Init(GPIOE, &GPIO_InitStructure); \
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
82 } while (0)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
83
15
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
84 #if 0
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
85 #define OWDELAY_A delay(6) /* 6 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
86 #define OWDELAY_B delay(64) /* 64 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
87 #define OWDELAY_C delay(60) /* 60 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
88 #define OWDELAY_D delay(10) /* 10 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
89 #define OWDELAY_E delay(9) /* 9 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
90 #define OWDELAY_F delay(55) /* 55 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
91 #define OWDELAY_G /* 0 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
92 #define OWDELAY_H delay(480) /* 480 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
93 #define OWDELAY_I delay(70) /* 70 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
94 #define OWDELAY_J delay(410) /* 410 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
95 #else
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
96 /* As measured by the cro delay() is correct, but the code does not work and I don't understand why.
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
97 * We need to use delays 2/3 the expected amount.
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
98 * Possibly due to use of GPIO_Init(), however the STM32 lib doesn't seem to have a function to
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
99 * just set the GPIO mode.
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
100 */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
101 #define OWDELAY_A delay(4) /* 6 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
102 #define OWDELAY_B delay(43) /* 64 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
103 #define OWDELAY_C delay(40) /* 60 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
104 #define OWDELAY_D delay(7) /* 10 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
105 #define OWDELAY_E delay(6) /* 9 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
106 #define OWDELAY_F delay(37) /* 55 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
107 #define OWDELAY_G /* 0 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
108 #define OWDELAY_H delay(320) /* 480 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
109 #define OWDELAY_I delay(47) /* 70 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
110 #define OWDELAY_J delay(273) /* 410 usec */
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
111 #endif
b12881051261 Use corrected delay() routine.
Daniel O'Connor <darius@dons.net.au>
parents: 13
diff changeset
112 //#define OW_DEBUG
13
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
113 #ifdef OW_DEBUG
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
114 #define OWPUTS(x) puts(x)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
115 #define OWPUTSP(x) puts(x)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
116 #define OWPRINTFP(fmt, ...) printf(fmt, ## __VA_ARGS__)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
117 #else
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
118 #define OWPUTS(x)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
119 #define OWPUTSP(x)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
120 #define OWPRINTFP(fmt, ...)
96c345d304af Add 1wire code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
121 #endif