stm32temp: libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system

annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c @ 85:18b154c447bb

Add note about 1-wire wiring

author	Daniel O'Connor <darius@dons.net.au>
date	Thu, 12 Mar 2015 23:22:11 +1030
parents	c59513fd84fb
children

rev	line source
0 c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	2 ******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	3 * @file system_stm32f10x.c
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	4 * @author MCD Application Team
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	5 * @version V3.5.0
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	6 * @date 08-April-2011
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	8 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	9 * 1. This file provides two functions and one global variable to be called from
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	10 * user application:
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	12 * factors, AHB/APBx prescalers and Flash settings).
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	13 * This function is called at startup just after reset and
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	14 * before branch to main program. This call is made inside
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	15 * the "startup_stm32f10x_xx.s" file.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	16 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	18 * by the user application to setup the SysTick
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	19 * timer or configure other parameters.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	20 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	22 * be called whenever the core clock is changed
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	23 * during program execution.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	24 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	26 * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	27 * configure the system clock before to branch to main program.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	28 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	29 * 3. If the system clock source selected by user fails to startup, the SystemInit()
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	30 * function will do nothing and HSI still used as system clock source. User can
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	31 * add some code to deal with this issue inside the SetSysClock() function.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	32 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	33 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	34 * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	35 * When HSE is used as system clock source, directly or through PLL, and you
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	36 * are using different crystal you have to adapt the HSE value to your own
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	37 * configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	38 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	39 ******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	40 * @attention
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	41 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	42 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	43 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	44 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	45 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	46 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	47 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	48 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	49 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	50 ******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	51 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	52
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	53 /** @addtogroup CMSIS
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	54 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	55 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	56
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	57 /** @addtogroup stm32f10x_system
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	58 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	59 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	60
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	61 /** @addtogroup STM32F10x_System_Private_Includes
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	62 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	63 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	64
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	65 #include "stm32f10x.h"
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	66
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	67 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	68 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	69 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	70
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	71 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	72 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	73 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	74
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	75 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	76 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	77 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	78
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	79 /** @addtogroup STM32F10x_System_Private_Defines
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	80 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	81 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	82
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	83 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	84 frequency (after reset the HSI is used as SYSCLK source)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	85
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	86 IMPORTANT NOTE:
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	87 ==============
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	88 1. After each device reset the HSI is used as System clock source.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	89
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	90 2. Please make sure that the selected System clock doesn't exceed your device's
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	91 maximum frequency.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	92
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	93 3. If none of the define below is enabled, the HSI is used as System clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	94 source.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	95
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	96 4. The System clock configuration functions provided within this file assume that:
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	97 - For Low, Medium and High density Value line devices an external 8MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	98 crystal is used to drive the System clock.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	99 - For Low, Medium and High density devices an external 8MHz crystal is
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	100 used to drive the System clock.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	101 - For Connectivity line devices an external 25MHz crystal is used to drive
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	102 the System clock.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	103 If you are using different crystal you have to adapt those functions accordingly.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	104 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	105
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	106 #if defined (STM32F10X_LD_VL) \|\| (defined STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	107 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	108 #define SYSCLK_FREQ_24MHz 24000000
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	109 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	110 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	111 /* #define SYSCLK_FREQ_24MHz 24000000 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	112 /* #define SYSCLK_FREQ_36MHz 36000000 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	113 /* #define SYSCLK_FREQ_48MHz 48000000 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	114 /* #define SYSCLK_FREQ_56MHz 56000000 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	115 #define SYSCLK_FREQ_72MHz 72000000
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	116 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	117
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	118 /*!< Uncomment the following line if you need to use external SRAM mounted
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	119 on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	120 STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	121 #if defined (STM32F10X_HD) \|\| (defined STM32F10X_XL) \|\| (defined STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	122 /* #define DATA_IN_ExtSRAM */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	123 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	124
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	125 /*!< Uncomment the following line if you need to relocate your vector Table in
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	126 Internal SRAM. */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	127 /* #define VECT_TAB_SRAM */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	128 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	129 This value must be a multiple of 0x200. */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	130
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	131
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	132 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	133 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	134 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	135
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	136 /** @addtogroup STM32F10x_System_Private_Macros
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	137 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	138 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	139
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	140 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	141 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	142 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	143
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	144 /** @addtogroup STM32F10x_System_Private_Variables
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	145 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	146 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	147
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	148 /*******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	149 * Clock Definitions
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	150 *******************************************************************************/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	151 #ifdef SYSCLK_FREQ_HSE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	152 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	153 #elif defined SYSCLK_FREQ_24MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	154 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	155 #elif defined SYSCLK_FREQ_36MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	156 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	157 #elif defined SYSCLK_FREQ_48MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	158 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	159 #elif defined SYSCLK_FREQ_56MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	160 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	161 #elif defined SYSCLK_FREQ_72MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	162 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	163 #else /!< HSI Selected as System Clock source /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	164 uint32_t SystemCoreClock = HSI_VALUE; /!< System Clock Frequency (Core Clock) /
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	165 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	166
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	168 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	169 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	170 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	171
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	173 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	174 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	175
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	176 static void SetSysClock(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	177
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	178 #ifdef SYSCLK_FREQ_HSE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	179 static void SetSysClockToHSE(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	180 #elif defined SYSCLK_FREQ_24MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	181 static void SetSysClockTo24(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	182 #elif defined SYSCLK_FREQ_36MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	183 static void SetSysClockTo36(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	184 #elif defined SYSCLK_FREQ_48MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	185 static void SetSysClockTo48(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	186 #elif defined SYSCLK_FREQ_56MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	187 static void SetSysClockTo56(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	188 #elif defined SYSCLK_FREQ_72MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	189 static void SetSysClockTo72(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	190 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	191
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	192 #ifdef DATA_IN_ExtSRAM
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	193 static void SystemInit_ExtMemCtl(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	194 #endif /* DATA_IN_ExtSRAM */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	195
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	196 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	197 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	198 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	199
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	200 /** @addtogroup STM32F10x_System_Private_Functions
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	201 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	202 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	203
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	204 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	205 * @brief Setup the microcontroller system
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	206 * Initialize the Embedded Flash Interface, the PLL and update the
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	207 * SystemCoreClock variable.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	208 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	209 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	210 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	211 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	212 void SystemInit (void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	213 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	214 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	215 /* Set HSION bit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	216 RCC->CR \|= (uint32_t)0x00000001;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	217
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	218 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	219 #ifndef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	220 RCC->CFGR &= (uint32_t)0xF8FF0000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	221 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	222 RCC->CFGR &= (uint32_t)0xF0FF0000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	223 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	224
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	225 /* Reset HSEON, CSSON and PLLON bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	226 RCC->CR &= (uint32_t)0xFEF6FFFF;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	227
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	228 /* Reset HSEBYP bit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	229 RCC->CR &= (uint32_t)0xFFFBFFFF;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	230
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	231 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	232 RCC->CFGR &= (uint32_t)0xFF80FFFF;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	233
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	234 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	235 /* Reset PLL2ON and PLL3ON bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	236 RCC->CR &= (uint32_t)0xEBFFFFFF;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	237
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	238 /* Disable all interrupts and clear pending bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	239 RCC->CIR = 0x00FF0000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	240
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	241 /* Reset CFGR2 register */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	242 RCC->CFGR2 = 0x00000000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	243 #elif defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	244 /* Disable all interrupts and clear pending bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	245 RCC->CIR = 0x009F0000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	246
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	247 /* Reset CFGR2 register */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	248 RCC->CFGR2 = 0x00000000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	249 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	250 /* Disable all interrupts and clear pending bits */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	251 RCC->CIR = 0x009F0000;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	252 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	253
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	254 #if defined (STM32F10X_HD) \|\| (defined STM32F10X_XL) \|\| (defined STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	255 #ifdef DATA_IN_ExtSRAM
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	256 SystemInit_ExtMemCtl();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	257 #endif /* DATA_IN_ExtSRAM */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	258 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	259
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	260 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	261 /* Configure the Flash Latency cycles and enable prefetch buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	262 SetSysClock();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	263
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	264 #ifdef VECT_TAB_SRAM
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	265 SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	266 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	267 SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	268 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	269 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	270
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	271 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	272 * @brief Update SystemCoreClock variable according to Clock Register Values.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	273 * The SystemCoreClock variable contains the core clock (HCLK), it can
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	274 * be used by the user application to setup the SysTick timer or configure
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	275 * other parameters.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	276 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	277 * @note Each time the core clock (HCLK) changes, this function must be called
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	278 * to update SystemCoreClock variable value. Otherwise, any configuration
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	279 * based on this variable will be incorrect.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	280 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	281 * @note - The system frequency computed by this function is not the real
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	282 * frequency in the chip. It is calculated based on the predefined
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	283 * constant and the selected clock source:
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	284 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	285 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	286 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	287 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	288 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	289 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	290 * or HSI_VALUE(*) multiplied by the PLL factors.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	291 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	292 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	293 * 8 MHz) but the real value may vary depending on the variations
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	294 * in voltage and temperature.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	295 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	296 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	297 * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	298 * that HSE_VALUE is same as the real frequency of the crystal used.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	299 * Otherwise, this function may have wrong result.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	300 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	301 * - The result of this function could be not correct when using fractional
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	302 * value for HSE crystal.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	303 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	304 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	305 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	306 void SystemCoreClockUpdate (void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	307 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	308 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	309
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	310 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	311 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	312 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	313
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	314 #if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	315 uint32_t prediv1factor = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	317
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	318 /* Get SYSCLK source -------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	319 tmp = RCC->CFGR & RCC_CFGR_SWS;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	320
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	321 switch (tmp)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	322 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	323 case 0x00: /* HSI used as system clock */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	324 SystemCoreClock = HSI_VALUE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	325 break;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	326 case 0x04: /* HSE used as system clock */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	327 SystemCoreClock = HSE_VALUE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	328 break;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	329 case 0x08: /* PLL used as system clock */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	330
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	331 /* Get PLL clock source and multiplication factor ----------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	333 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	334
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	335 #ifndef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	336 pllmull = ( pllmull >> 18) + 2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	337
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	338 if (pllsource == 0x00)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	339 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	340 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	341 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	342 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	343 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	344 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	345 #if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| (defined STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	347 /* HSE oscillator clock selected as PREDIV1 clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	348 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	349 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	350 /* HSE selected as PLL clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	351 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	352 {/* HSE oscillator clock divided by 2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	353 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	354 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	355 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	356 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	357 SystemCoreClock = HSE_VALUE * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	358 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	359 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	360 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	361 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	362 pllmull = pllmull >> 18;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	363
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	364 if (pllmull != 0x0D)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	365 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	366 pllmull += 2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	367 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	368 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	369 { /* PLL multiplication factor = PLL input clock * 6.5 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	370 pllmull = 13 / 2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	371 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	372
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	373 if (pllsource == 0x00)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	374 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	375 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	376 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	377 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	378 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	379 {/* PREDIV1 selected as PLL clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	380
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	381 /* Get PREDIV1 clock source and division factor */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	384
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	385 if (prediv1source == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	386 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	387 /* HSE oscillator clock selected as PREDIV1 clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	388 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	389 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	390 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	391 {/* PLL2 clock selected as PREDIV1 clock entry */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	392
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	393 /* Get PREDIV2 division factor and PLL2 multiplication factor */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	396 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	397 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	398 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	399 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	400 break;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	401
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	402 default:
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	403 SystemCoreClock = HSI_VALUE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	404 break;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	405 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	406
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	407 /* Compute HCLK clock frequency ----------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	408 /* Get HCLK prescaler */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	409 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	410 /* HCLK clock frequency */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	411 SystemCoreClock >>= tmp;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	412 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	413
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	414 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	415 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	416 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	417 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	418 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	419 static void SetSysClock(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	420 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	421 #ifdef SYSCLK_FREQ_HSE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	422 SetSysClockToHSE();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	423 #elif defined SYSCLK_FREQ_24MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	424 SetSysClockTo24();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	425 #elif defined SYSCLK_FREQ_36MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	426 SetSysClockTo36();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	427 #elif defined SYSCLK_FREQ_48MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	428 SetSysClockTo48();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	429 #elif defined SYSCLK_FREQ_56MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	430 SetSysClockTo56();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	431 #elif defined SYSCLK_FREQ_72MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	432 SetSysClockTo72();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	433 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	434
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	435 /* If none of the define above is enabled, the HSI is used as System clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	436 source (default after reset) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	437 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	438
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	439 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	440 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	441 * before jump to __main
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	442 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	443 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	444 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	445 #ifdef DATA_IN_ExtSRAM
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	446 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	447 * @brief Setup the external memory controller.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	448 * Called in startup_stm32f10x_xx.s/.c before jump to main.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	449 * This function configures the external SRAM mounted on STM3210E-EVAL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	450 * board (STM32 High density devices). This SRAM will be used as program
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	451 * data memory (including heap and stack).
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	452 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	453 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	454 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	455 void SystemInit_ExtMemCtl(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	456 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	458 required, then adjust the Register Addresses */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	459
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	460 /* Enable FSMC clock */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	461 RCC->AHBENR = 0x00000114;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	462
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	463 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	464 RCC->APB2ENR = 0x000001E0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	465
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	466 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	467 /---------------- SRAM Address lines configuration -------------------------/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	468 /---------------- NOE and NWE configuration --------------------------------/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	469 /---------------- NE3 configuration ----------------------------------------/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	470 /---------------- NBL0, NBL1 configuration ---------------------------------/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	471
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	472 GPIOD->CRL = 0x44BB44BB;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	473 GPIOD->CRH = 0xBBBBBBBB;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	474
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	475 GPIOE->CRL = 0xB44444BB;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	476 GPIOE->CRH = 0xBBBBBBBB;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	477
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	478 GPIOF->CRL = 0x44BBBBBB;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	479 GPIOF->CRH = 0xBBBB4444;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	480
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	481 GPIOG->CRL = 0x44BBBBBB;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	482 GPIOG->CRH = 0x44444B44;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	483
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	484 /---------------- FSMC Configuration ---------------------------------------/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	485 /---------------- Enable FSMC Bank1_SRAM Bank ------------------------------/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	486
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	487 FSMC_Bank1->BTCR[4] = 0x00001011;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	488 FSMC_Bank1->BTCR[5] = 0x00000200;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	489 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	490 #endif /* DATA_IN_ExtSRAM */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	491
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	492 #ifdef SYSCLK_FREQ_HSE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	493 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	494 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	495 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	496 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	497 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	498 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	499 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	500 static void SetSysClockToHSE(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	501 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	502 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	503
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	504 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	505 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	506 RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	507
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	508 /* Wait till HSE is ready and if Time out is reached exit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	509 do
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	510 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	511 HSEStatus = RCC->CR & RCC_CR_HSERDY;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	512 StartUpCounter++;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	513 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	514
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	515 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	516 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	517 HSEStatus = (uint32_t)0x01;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	518 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	519 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	520 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	521 HSEStatus = (uint32_t)0x00;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	522 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	523
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	524 if (HSEStatus == (uint32_t)0x01)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	525 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	526
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	528 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	529 FLASH->ACR \|= FLASH_ACR_PRFTBE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	530
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	531 /* Flash 0 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	532 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	533
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	534 #ifndef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	535 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	536 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	537 if (HSE_VALUE <= 24000000)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	538 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	539 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	540 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	541 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	542 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	543 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	544 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	545 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	546 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	547
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	548 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	549 RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	550
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	551 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	552 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	553
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	554 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	555 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	556
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	557 /* Select HSE as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	558 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	559 RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_HSE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	560
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	561 /* Wait till HSE is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	562 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	563 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	564 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	565 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	566 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	567 { /* If HSE fails to start-up, the application will have wrong clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	568 configuration. User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	569 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	570 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	571 #elif defined SYSCLK_FREQ_24MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	572 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	573 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	574 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	575 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	576 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	577 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	578 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	579 static void SetSysClockTo24(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	580 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	581 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	582
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	583 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	584 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	585 RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	586
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	587 /* Wait till HSE is ready and if Time out is reached exit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	588 do
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	589 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	590 HSEStatus = RCC->CR & RCC_CR_HSERDY;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	591 StartUpCounter++;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	592 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	593
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	594 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	595 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	596 HSEStatus = (uint32_t)0x01;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	597 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	598 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	599 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	600 HSEStatus = (uint32_t)0x00;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	601 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	602
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	603 if (HSEStatus == (uint32_t)0x01)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	604 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	606 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	607 FLASH->ACR \|= FLASH_ACR_PRFTBE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	608
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	609 /* Flash 0 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	610 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	611 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	612 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	613
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	614 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	615 RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	616
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	617 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	618 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	619
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	620 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	621 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	622
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	623 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	624 /* Configure PLLs ------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	625 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	626 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	627 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	628 RCC_CFGR_PLLMULL6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	629
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	630 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	631 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	632 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	633 RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	634 RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	635 RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV10);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	636
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	637 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	638 RCC->CR \|= RCC_CR_PLL2ON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	639 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	640 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	641 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	642 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	643 #elif defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	644 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	645 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	646 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1_Div2 \| RCC_CFGR_PLLMULL6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	647 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	648 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	649 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	650 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLXTPRE_HSE_Div2 \| RCC_CFGR_PLLMULL6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	651 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	652
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	653 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	654 RCC->CR \|= RCC_CR_PLLON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	655
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	656 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	657 while((RCC->CR & RCC_CR_PLLRDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	658 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	659 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	660
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	661 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	662 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	663 RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	664
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	665 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	666 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	667 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	668 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	669 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	670 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	671 { /* If HSE fails to start-up, the application will have wrong clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	672 configuration. User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	673 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	674 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	675 #elif defined SYSCLK_FREQ_36MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	676 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	677 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	678 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	679 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	680 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	681 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	682 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	683 static void SetSysClockTo36(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	684 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	685 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	686
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	687 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	688 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	689 RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	690
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	691 /* Wait till HSE is ready and if Time out is reached exit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	692 do
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	693 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	694 HSEStatus = RCC->CR & RCC_CR_HSERDY;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	695 StartUpCounter++;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	696 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	697
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	698 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	699 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	700 HSEStatus = (uint32_t)0x01;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	701 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	702 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	703 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	704 HSEStatus = (uint32_t)0x00;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	705 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	706
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	707 if (HSEStatus == (uint32_t)0x01)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	708 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	709 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	710 FLASH->ACR \|= FLASH_ACR_PRFTBE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	711
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	712 /* Flash 1 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	713 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	714 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	715
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	716 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	717 RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	718
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	719 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	720 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	721
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	722 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	723 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	724
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	725 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	726 /* Configure PLLs ------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	727
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	728 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	729 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	730 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	731 RCC_CFGR_PLLMULL9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	732
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	733 /!< PLL2 configuration: PLL2CLK = (HSE / 5) 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	734 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	735
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	736 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	737 RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	738 RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	739 RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV10);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	740
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	741 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	742 RCC->CR \|= RCC_CR_PLL2ON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	743 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	744 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	745 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	746 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	747
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	748 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	749 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	750 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	751 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLXTPRE_HSE_Div2 \| RCC_CFGR_PLLMULL9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	752 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	753
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	754 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	755 RCC->CR \|= RCC_CR_PLLON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	756
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	757 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	758 while((RCC->CR & RCC_CR_PLLRDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	759 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	760 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	761
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	762 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	763 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	764 RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	765
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	766 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	767 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	768 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	769 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	770 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	771 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	772 { /* If HSE fails to start-up, the application will have wrong clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	773 configuration. User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	774 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	775 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	776 #elif defined SYSCLK_FREQ_48MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	777 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	778 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	779 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	780 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	781 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	782 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	783 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	784 static void SetSysClockTo48(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	785 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	786 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	787
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	788 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	789 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	790 RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	791
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	792 /* Wait till HSE is ready and if Time out is reached exit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	793 do
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	794 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	795 HSEStatus = RCC->CR & RCC_CR_HSERDY;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	796 StartUpCounter++;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	797 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	798
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	799 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	800 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	801 HSEStatus = (uint32_t)0x01;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	802 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	803 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	804 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	805 HSEStatus = (uint32_t)0x00;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	806 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	807
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	808 if (HSEStatus == (uint32_t)0x01)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	809 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	810 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	811 FLASH->ACR \|= FLASH_ACR_PRFTBE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	812
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	813 /* Flash 1 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	814 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	815 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	816
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	817 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	818 RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	819
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	820 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	821 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	822
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	823 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	824 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	825
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	826 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	827 /* Configure PLLs ------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	828 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	829 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	830
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	831 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	832 RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	833 RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	834 RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	835
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	836 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	837 RCC->CR \|= RCC_CR_PLL2ON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	838 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	839 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	840 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	841 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	842
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	843
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	844 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	845 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	846 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	847 RCC_CFGR_PLLMULL6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	848 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	849 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	850 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	851 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLMULL6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	852 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	853
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	854 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	855 RCC->CR \|= RCC_CR_PLLON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	856
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	857 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	858 while((RCC->CR & RCC_CR_PLLRDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	859 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	860 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	861
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	862 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	863 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	864 RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	865
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	866 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	867 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	868 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	869 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	870 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	871 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	872 { /* If HSE fails to start-up, the application will have wrong clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	873 configuration. User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	874 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	875 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	876
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	877 #elif defined SYSCLK_FREQ_56MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	878 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	879 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	880 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	881 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	882 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	883 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	884 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	885 static void SetSysClockTo56(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	886 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	887 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	888
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	889 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	890 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	891 RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	892
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	893 /* Wait till HSE is ready and if Time out is reached exit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	894 do
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	895 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	896 HSEStatus = RCC->CR & RCC_CR_HSERDY;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	897 StartUpCounter++;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	898 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	899
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	900 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	901 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	902 HSEStatus = (uint32_t)0x01;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	903 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	904 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	905 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	906 HSEStatus = (uint32_t)0x00;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	907 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	908
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	909 if (HSEStatus == (uint32_t)0x01)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	910 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	911 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	912 FLASH->ACR \|= FLASH_ACR_PRFTBE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	913
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	914 /* Flash 2 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	915 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	916 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	917
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	918 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	919 RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	920
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	921 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	922 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	923
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	924 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	925 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	926
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	927 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	928 /* Configure PLLs ------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	929 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	930 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	931
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	932 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	933 RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	934 RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	935 RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	936
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	937 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	938 RCC->CR \|= RCC_CR_PLL2ON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	939 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	940 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	941 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	942 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	943
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	944
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	945 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	946 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	947 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	948 RCC_CFGR_PLLMULL7);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	949 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	950 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	951 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	952 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLMULL7);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	953
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	954 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	955
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	956 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	957 RCC->CR \|= RCC_CR_PLLON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	958
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	959 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	960 while((RCC->CR & RCC_CR_PLLRDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	961 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	962 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	963
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	964 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	965 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	966 RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	967
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	968 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	969 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	970 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	971 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	972 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	973 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	974 { /* If HSE fails to start-up, the application will have wrong clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	975 configuration. User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	976 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	977 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	978
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	979 #elif defined SYSCLK_FREQ_72MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	980 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	981 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	982 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	983 * @note This function should be used only after reset.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	984 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	985 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	986 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	987 static void SetSysClockTo72(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	988 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	989 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	990
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	991 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	992 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	993 RCC->CR \|= ((uint32_t)RCC_CR_HSEON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	994
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	995 /* Wait till HSE is ready and if Time out is reached exit */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	996 do
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	997 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	998 HSEStatus = RCC->CR & RCC_CR_HSERDY;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	999 StartUpCounter++;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1000 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1001
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1002 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1003 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1004 HSEStatus = (uint32_t)0x01;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1005 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1006 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1007 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1008 HSEStatus = (uint32_t)0x00;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1009 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1010
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1011 if (HSEStatus == (uint32_t)0x01)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1012 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1013 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1014 FLASH->ACR \|= FLASH_ACR_PRFTBE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1015
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1016 /* Flash 2 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1017 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1018 FLASH->ACR \|= (uint32_t)FLASH_ACR_LATENCY_2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1019
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1020
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1021 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1022 RCC->CFGR \|= (uint32_t)RCC_CFGR_HPRE_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1023
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1024 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1025 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE2_DIV1;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1026
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1027 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1028 RCC->CFGR \|= (uint32_t)RCC_CFGR_PPRE1_DIV2;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1029
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1030 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1031 /* Configure PLLs ------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1032 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1033 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1034
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1035 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1036 RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1037 RCC->CFGR2 \|= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 \| RCC_CFGR2_PLL2MUL8 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1038 RCC_CFGR2_PREDIV1SRC_PLL2 \| RCC_CFGR2_PREDIV1_DIV5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1039
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1040 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1041 RCC->CR \|= RCC_CR_PLL2ON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1042 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1043 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1044 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1045 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1046
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1047
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1048 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1049 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1050 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1051 RCC_CFGR_PLLMULL9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1052 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1053 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1054 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \|
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1055 RCC_CFGR_PLLMULL));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1056 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_HSE \| RCC_CFGR_PLLMULL9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1057 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1058
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1059 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1060 RCC->CR \|= RCC_CR_PLLON;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1061
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1062 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1063 while((RCC->CR & RCC_CR_PLLRDY) == 0)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1064 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1065 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1066
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1067 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1068 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1069 RCC->CFGR \|= (uint32_t)RCC_CFGR_SW_PLL;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1070
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1071 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1072 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1073 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1074 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1075 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1076 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1077 { /* If HSE fails to start-up, the application will have wrong clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1078 configuration. User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1079 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1080 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1081 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1082
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1083 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1084 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1085 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1086
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1087 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1088 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1089 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1090
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1091 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1092 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1093 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1094 /***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

Mercurial > ~darius > hgwebdir.cgi > stm32temp

annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c @ 85:18b154c447bb