stm32temp: libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC

annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c @ 85:18b154c447bb

Add note about 1-wire wiring

author	Daniel O'Connor <darius@dons.net.au>
date	Thu, 12 Mar 2015 23:22:11 +1030
parents	c59513fd84fb
children

rev	line source
0 c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	1 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	2 ******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	3 * @file RCC/RCC_ClockConfig/main.c
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	4 * @author MCD Application Team
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	5 * @version V3.5.0
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	6 * @date 08-April-2011
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	7 * @brief Main program body.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	8 ******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	9 * @attention
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	10 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	17 *
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	18 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	19 ******************************************************************************
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	20 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	21
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	22 /* Includes ------------------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	23 #include "main.h"
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	24
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	25 /** @addtogroup STM32F10x_StdPeriph_Examples
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	26 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	27 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	28
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	29
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	30 /** @addtogroup RCC_ClockConfig
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	31 * @{
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	32 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	33
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	34 /* Private typedef -----------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	35 /* Private define ------------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	36 #define DELAY_COUNT 0x3FFFF
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	37
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	38 /* Private macro -------------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	39 /* Private variables ---------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	40 GPIO_InitTypeDef GPIO_InitStructure;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	41 RCC_ClocksTypeDef RCC_ClockFreq;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	42 ErrorStatus HSEStartUpStatus;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	43
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	44 /* Private function prototypes -----------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	45 void NVIC_Configuration(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	46 void Delay(__IO uint32_t nCount);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	47
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	48 void SetSysClock(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	49 #ifdef SYSCLK_HSE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	50 void SetSysClockToHSE(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	51 #elif defined SYSCLK_FREQ_24MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	52 void SetSysClockTo24(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	53 #elif defined SYSCLK_FREQ_36MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	54 void SetSysClockTo36(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	55 #elif defined SYSCLK_FREQ_48MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	56 void SetSysClockTo48(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	57 #elif defined SYSCLK_FREQ_56MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	58 void SetSysClockTo56(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	59 #elif defined SYSCLK_FREQ_72MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	60 void SetSysClockTo72(void);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	61 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	62
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	63 /* Private functions ---------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	64
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	65 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	66 * @brief Main program.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	67 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	68 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	69 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	70 int main(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	71 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	72 /*!< At this stage the microcontroller clock setting is already configured,
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	73 this is done through SystemInit() function which is called from startup
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	74 file (startup_stm32f10x_xx.s) before to branch to application main.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	75 To reconfigure the default setting of SystemInit() function, refer to
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	76 system_stm32f10x.c file
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	77 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	78
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	79 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	80 SetSysClock();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	81
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	82 /* This function fills the RCC_ClockFreq structure with the current
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	83 frequencies of different on chip clocks (for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	84 RCC_GetClocksFreq(&RCC_ClockFreq);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	85
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	86 /* Enable Clock Security System(CSS): this will generate an NMI exception
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	87 when HSE clock fails */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	88 RCC_ClockSecuritySystemCmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	89
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	90 /* NVIC configuration ------------------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	91 NVIC_Configuration();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	92
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	93 /* Initialize Leds mounted on STM3210X-EVAL board --------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	94 STM_EVAL_LEDInit(LED1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	95 STM_EVAL_LEDInit(LED2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	96 STM_EVAL_LEDInit(LED3);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	97 STM_EVAL_LEDInit(LED4);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	98
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	99 /* Output HSE clock on MCO pin ---------------------------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	100 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	101
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	102 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	103 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	104 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	105 GPIO_Init(GPIOA, &GPIO_InitStructure);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	106 RCC_MCOConfig(RCC_MCO_HSE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	107
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	108 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	109 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	110 /* Toggle LED1 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	111 STM_EVAL_LEDToggle(LED1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	112 /* Insert delay */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	113 Delay(DELAY_COUNT);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	114
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	115 /* Toggle LED2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	116 STM_EVAL_LEDToggle(LED2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	117 /* Insert delay */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	118 Delay(DELAY_COUNT);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	119
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	120 /* Toggle LED3 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	121 STM_EVAL_LEDToggle(LED3);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	122 /* Insert delay */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	123 Delay(DELAY_COUNT);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	124
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	125 /* Toggle LED4 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	126 STM_EVAL_LEDToggle(LED4);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	127 /* Insert a delay */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	128 Delay(DELAY_COUNT);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	129 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	130 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	131
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	132 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	133 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	134 * prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	135 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	136 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	137 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	138 void SetSysClock(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	139 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	140 /* The System clock configuration functions defined below assume that:
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	141 - For Low, Medium and High density devices an external 8MHz crystal is
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	142 used to drive the System clock.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	143 - For Connectivity line devices an external 25MHz crystal is used to drive
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	144 the System clock.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	145 If you are using different crystal you have to adapt those functions accordingly.*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	146
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	147 #if defined SYSCLK_HSE
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	148 SetSysClockToHSE();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	149 #elif defined SYSCLK_FREQ_24MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	150 SetSysClockTo24();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	151 #elif defined SYSCLK_FREQ_36MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	152 SetSysClockTo36();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	153 #elif defined SYSCLK_FREQ_48MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	154 SetSysClockTo48();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	155 #elif defined SYSCLK_FREQ_56MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	156 SetSysClockTo56();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	157 #elif defined SYSCLK_FREQ_72MHz
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	158 SetSysClockTo72();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	159 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	160
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	161 /* If none of the define above is enabled, the HSI is used as System clock
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	162 source (default after reset) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	163 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	164
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	165 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	166 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	167 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	168 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	169 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	170 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	171 void SetSysClockToHSE(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	172 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	173 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	174 /* RCC system reset(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	175 RCC_DeInit();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	176
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	177 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	178 RCC_HSEConfig(RCC_HSE_ON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	179
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	180 /* Wait till HSE is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	181 HSEStartUpStatus = RCC_WaitForHSEStartUp();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	182
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	183 if (HSEStartUpStatus == SUCCESS)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	184 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	185 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	186 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	187 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	188
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	189 #ifndef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	190 /* Flash 0 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	191 FLASH_SetLatency(FLASH_Latency_0);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	192 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	193 if (HSE_Value <= 24000000)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	194 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	195 /* Flash 0 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	196 FLASH_SetLatency(FLASH_Latency_0);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	197 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	198 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	199 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	200 /* Flash 1 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	201 FLASH_SetLatency(FLASH_Latency_1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	202 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	203
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	204 #endif /* STM32F10X_CL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	205 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	206
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	207 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	208 RCC_HCLKConfig(RCC_SYSCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	209
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	210 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	211 RCC_PCLK2Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	212
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	213 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	214 RCC_PCLK1Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	215
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	216 /* Select HSE as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	217 RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	218
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	219 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	220 while (RCC_GetSYSCLKSource() != 0x04)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	221 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	222 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	223 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	224 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	225 { /* If HSE fails to start-up, the application will have wrong clock configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	226 User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	227
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	228 /* Go to infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	229 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	230 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	231 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	232 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	233 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	234
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	235 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	236 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	237 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	238 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	239 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	240 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	241 void SetSysClockTo24(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	242 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	243 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	244 /* RCC system reset(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	245 RCC_DeInit();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	246
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	247 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	248 RCC_HSEConfig(RCC_HSE_ON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	249
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	250 /* Wait till HSE is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	251 HSEStartUpStatus = RCC_WaitForHSEStartUp();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	252
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	253 if (HSEStartUpStatus == SUCCESS)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	254 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	255 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	256 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	257 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	258
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	259 /* Flash 0 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	260 FLASH_SetLatency(FLASH_Latency_0);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	261 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	262
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	263 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	264 RCC_HCLKConfig(RCC_SYSCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	265
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	266 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	267 RCC_PCLK2Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	268
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	269 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	270 RCC_PCLK1Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	271
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	272 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	273 /* Configure PLLs *********************************************************/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	274 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	275 RCC_PREDIV2Config(RCC_PREDIV2_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	276 RCC_PLL2Config(RCC_PLL2Mul_8);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	277
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	278 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	279 RCC_PLL2Cmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	280
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	281 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	282 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	283 {}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	284
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	285 /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	286 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	287 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	288 #elif defined STM32F10X_LD_VL \|\| defined STM32F10X_MD_VL \|\| defined STM32F10X_HD_VL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	289 /* PLLCLK = (8MHz/2) * 6 = 24 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	290 RCC_PREDIV1Config(RCC_PREDIV1_Source_HSE, RCC_PREDIV1_Div2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	291 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	292 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	293 /* PLLCLK = 8MHz * 3 = 24 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	294 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	295 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	296
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	297 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	298 RCC_PLLCmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	299
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	300 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	301 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	302 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	303 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	304
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	305 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	306 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	307
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	308 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	309 while (RCC_GetSYSCLKSource() != 0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	310 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	311 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	312 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	313 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	314 { /* If HSE fails to start-up, the application will have wrong clock configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	315 User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	316
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	317 /* Go to infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	318 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	319 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	320 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	321 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	322 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	323 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	324 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	325 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	326 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	327 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	328 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	329 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	330 void SetSysClockTo36(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	331 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	332 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	333 /* RCC system reset(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	334 RCC_DeInit();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	335
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	336 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	337 RCC_HSEConfig(RCC_HSE_ON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	338
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	339 /* Wait till HSE is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	340 HSEStartUpStatus = RCC_WaitForHSEStartUp();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	341
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	342 if (HSEStartUpStatus == SUCCESS)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	343 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	344 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	345 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	346
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	347 /* Flash 1 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	348 FLASH_SetLatency(FLASH_Latency_1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	349
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	350 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	351 RCC_HCLKConfig(RCC_SYSCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	352
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	353 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	354 RCC_PCLK2Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	355
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	356 /* PCLK1 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	357 RCC_PCLK1Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	358
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	359 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	360 /* Configure PLLs *********************************************************/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	361 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	362 RCC_PREDIV2Config(RCC_PREDIV2_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	363 RCC_PLL2Config(RCC_PLL2Mul_8);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	364
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	365 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	366 RCC_PLL2Cmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	367
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	368 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	369 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	370 {}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	371
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	372 /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	373 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div10);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	374 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	375 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	376 /* PLLCLK = (8MHz / 2) * 9 = 36 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	377 RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	378 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	379
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	380 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	381 RCC_PLLCmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	382
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	383 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	384 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	385 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	386 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	387
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	388 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	389 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	390
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	391 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	392 while (RCC_GetSYSCLKSource() != 0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	393 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	394 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	395 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	396 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	397 { /* If HSE fails to start-up, the application will have wrong clock configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	398 User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	399
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	400 /* Go to infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	401 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	402 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	403 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	404 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	405 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	406
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	407 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	408 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	409 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	410 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	411 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	412 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	413 void SetSysClockTo48(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	414 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	415 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	416 /* RCC system reset(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	417 RCC_DeInit();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	418
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	419 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	420 RCC_HSEConfig(RCC_HSE_ON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	421
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	422 /* Wait till HSE is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	423 HSEStartUpStatus = RCC_WaitForHSEStartUp();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	424
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	425 if (HSEStartUpStatus == SUCCESS)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	426 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	427 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	428 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	429
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	430 /* Flash 1 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	431 FLASH_SetLatency(FLASH_Latency_1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	432
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	433 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	434 RCC_HCLKConfig(RCC_SYSCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	435
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	436 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	437 RCC_PCLK2Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	438
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	439 /* PCLK1 = HCLK/2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	440 RCC_PCLK1Config(RCC_HCLK_Div2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	441
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	442 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	443 /* Configure PLLs *********************************************************/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	444 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	445 RCC_PREDIV2Config(RCC_PREDIV2_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	446 RCC_PLL2Config(RCC_PLL2Mul_8);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	447
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	448 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	449 RCC_PLL2Cmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	450
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	451 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	452 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	453 {}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	454
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	455 /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	456 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	457 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	458 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	459 /* PLLCLK = 8MHz * 6 = 48 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	460 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_6);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	461 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	462
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	463 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	464 RCC_PLLCmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	465
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	466 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	467 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	468 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	469 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	470
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	471 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	472 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	473
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	474 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	475 while (RCC_GetSYSCLKSource() != 0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	476 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	477 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	478 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	479 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	480 { /* If HSE fails to start-up, the application will have wrong clock configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	481 User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	482
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	483 /* Go to infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	484 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	485 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	486 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	487 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	488 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	489
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	490 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	491 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	492 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	493 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	494 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	495 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	496 void SetSysClockTo56(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	497 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	498 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	499 /* RCC system reset(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	500 RCC_DeInit();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	501
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	502 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	503 RCC_HSEConfig(RCC_HSE_ON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	504
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	505 /* Wait till HSE is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	506 HSEStartUpStatus = RCC_WaitForHSEStartUp();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	507
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	508 if (HSEStartUpStatus == SUCCESS)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	509 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	510 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	511 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	512
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	513 /* Flash 2 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	514 FLASH_SetLatency(FLASH_Latency_2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	515
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	516 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	517 RCC_HCLKConfig(RCC_SYSCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	518
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	519 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	520 RCC_PCLK2Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	521
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	522 /* PCLK1 = HCLK/2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	523 RCC_PCLK1Config(RCC_HCLK_Div2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	524
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	525 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	526 /* Configure PLLs *********************************************************/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	527 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	528 RCC_PREDIV2Config(RCC_PREDIV2_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	529 RCC_PLL2Config(RCC_PLL2Mul_8);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	530
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	531 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	532 RCC_PLL2Cmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	533
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	534 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	535 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	536 {}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	537
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	538 /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	539 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	540 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_7);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	541 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	542 /* PLLCLK = 8MHz * 7 = 56 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	543 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	544 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	545
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	546 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	547 RCC_PLLCmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	548
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	549 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	550 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	551 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	552 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	553
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	554 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	555 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	556
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	557 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	558 while (RCC_GetSYSCLKSource() != 0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	559 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	560 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	561 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	562 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	563 { /* If HSE fails to start-up, the application will have wrong clock configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	564 User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	565
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	566 /* Go to infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	567 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	568 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	569 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	570 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	571 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	572
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	573 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	574 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	575 * and PCLK1 prescalers.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	576 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	577 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	578 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	579 void SetSysClockTo72(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	580 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	581 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	582 /* RCC system reset(for debug purpose) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	583 RCC_DeInit();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	584
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	585 /* Enable HSE */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	586 RCC_HSEConfig(RCC_HSE_ON);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	587
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	588 /* Wait till HSE is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	589 HSEStartUpStatus = RCC_WaitForHSEStartUp();
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	590
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	591 if (HSEStartUpStatus == SUCCESS)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	592 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	593 /* Enable Prefetch Buffer */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	594 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	595
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	596 /* Flash 2 wait state */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	597 FLASH_SetLatency(FLASH_Latency_2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	598
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	599 /* HCLK = SYSCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	600 RCC_HCLKConfig(RCC_SYSCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	601
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	602 /* PCLK2 = HCLK */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	603 RCC_PCLK2Config(RCC_HCLK_Div1);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	604
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	605 /* PCLK1 = HCLK/2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	606 RCC_PCLK1Config(RCC_HCLK_Div2);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	607
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	608 #ifdef STM32F10X_CL
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	609 /* Configure PLLs *********************************************************/
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	610 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	611 RCC_PREDIV2Config(RCC_PREDIV2_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	612 RCC_PLL2Config(RCC_PLL2Mul_8);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	613
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	614 /* Enable PLL2 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	615 RCC_PLL2Cmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	616
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	617 /* Wait till PLL2 is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	618 while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	619 {}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	620
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	621 /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	622 RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	623 RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	624 #else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	625 /* PLLCLK = 8MHz * 9 = 72 MHz */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	626 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	627 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	628
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	629 /* Enable PLL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	630 RCC_PLLCmd(ENABLE);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	631
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	632 /* Wait till PLL is ready */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	633 while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	634 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	635 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	636
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	637 /* Select PLL as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	638 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	639
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	640 /* Wait till PLL is used as system clock source */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	641 while(RCC_GetSYSCLKSource() != 0x08)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	642 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	643 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	644 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	645 else
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	646 { /* If HSE fails to start-up, the application will have wrong clock configuration.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	647 User can add here some code to deal with this error */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	648
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	649 /* Go to infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	650 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	651 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	652 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	653 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	654 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	655
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	656 #endif /* STM32F10X_LD_VL && STM32F10X_MD_VL */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	657
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	658 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	659 * @brief Configures Vector Table base location.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	660 * @param None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	661 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	662 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	663 void NVIC_Configuration(void)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	664 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	665 NVIC_InitTypeDef NVIC_InitStructure;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	666
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	667 /* Enable and configure RCC global IRQ channel */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	668 NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	669 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	670 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	671 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	672 NVIC_Init(&NVIC_InitStructure);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	673 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	674
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	675 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	676 * @brief Inserts a delay time.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	677 * @param nCount: specifies the delay time length.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	678 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	679 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	680 void Delay(__IO uint32_t nCount)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	681 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	682 for(; nCount!= 0;nCount--);
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	683 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	684
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	685 #ifdef USE_FULL_ASSERT
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	686
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	687 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	688 * @brief Reports the name of the source file and the source line number
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	689 * where the assert_param error has occurred.
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	690 * @param file: pointer to the source file name
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	691 * @param line: assert_param error line source number
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	692 * @retval None
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	693 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	694 void assert_failed(uint8_t* file, uint32_t line)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	695 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	696 /* User can add his own implementation to report the file name and line number,
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	697 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	698
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	699 /* Infinite loop */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	700 while (1)
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	701 {
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	702 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	703 }
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	704
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	705 #endif
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	706
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	707 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	708 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	709 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	710
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	711 /**
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	712 * @}
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	713 */
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	714
c59513fd84fb Initial commit of STM32 test code. Daniel O'Connor <darius@dons.net.au> parents: diff changeset	715 /***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

Mercurial > ~darius > hgwebdir.cgi > stm32temp

annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c @ 85:18b154c447bb