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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/arm_arch.lsl @ 85:18b154c447bb

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Add note about 1-wire wiring
author Daniel O'Connor <darius@dons.net.au>
date Thu, 12 Mar 2015 23:22:11 +1030
parents c59513fd84fb
children
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1 ////////////////////////////////////////////////////////////////////////////
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2 //
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3 // File : arm_arch.lsl
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4 //
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5 // Version : @(#)arm_arch.lsl 1.4 09/04/17
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6 //
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7 // Description : Generic LSL file for ARM architectures
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8 //
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9 // Copyright 2008-2009 Altium BV
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10 //
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11 ////////////////////////////////////////////////////////////////////////////
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12
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13 #ifndef __STACK
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14 # define __STACK 32k
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15 #endif
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16 #ifndef __HEAP
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17 # define __HEAP 32k
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18 #endif
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19 #ifndef __STACK_FIQ
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20 # define __STACK_FIQ 8
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21 #endif
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22 #ifndef __STACK_IRQ
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23 # define __STACK_IRQ 8
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24 #endif
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25 #ifndef __STACK_SVC
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26 # define __STACK_SVC 8
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27 #endif
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28 #ifndef __STACK_ABT
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29 # define __STACK_ABT 8
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30 #endif
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31 #ifndef __STACK_UND
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32 # define __STACK_UND 8
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33 #endif
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34 #ifndef __PROCESSOR_MODE
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35 # define __PROCESSOR_MODE 0x1F /* SYS mode */
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36 #endif
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37 #ifndef __IRQ_BIT
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38 # define __IRQ_BIT 0x80 /* IRQ interrupts disabled */
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39 #endif
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40 #ifndef __FIQ_BIT
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41 # define __FIQ_BIT 0x40 /* FIQ interrupts disabled */
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42 #endif
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43
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44 #define __APPLICATION_MODE (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
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45
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46 #ifndef __VECTOR_TABLE_ROM_ADDR
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47 # define __VECTOR_TABLE_ROM_ADDR 0x00000000
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48 #endif
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49
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50 #ifndef __VECTOR_TABLE_RAM_ADDR
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51 # define __VECTOR_TABLE_RAM_ADDR 0x00000000
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52 #endif
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53
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54 #if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
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55 # ifndef __NR_OF_VECTORS
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56 # define __NR_OF_VECTORS 16
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57 # endif
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58 # define __VECTOR_TABLE_SIZE (__NR_OF_VECTORS * 4)
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59 #else
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60 # ifdef __PIC_VECTORS
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61 # define __VECTOR_TABLE_SIZE 64
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62 # else
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63 # ifdef __FIQ_HANDLER_INLINE
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64 # define __VECTOR_TABLE_SIZE 28
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65 # define __NR_OF_VECTORS 7
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66 # else
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67 # define __VECTOR_TABLE_SIZE 32
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68 # define __NR_OF_VECTORS 8
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69 # endif
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70 # endif
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71 #endif
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72
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73 #ifndef __VECTOR_TABLE_RAM_SPACE
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74 # undef __VECTOR_TABLE_RAM_COPY
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75 #endif
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76
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77 #ifndef __XVWBUF
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78 # define __XVWBUF 0 /* buffer used by CrossView Pro */
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79 #endif
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80
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81 #define BOUNDS_GROUP_NAME grp_bounds
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82 #define BOUNDS_GROUP_SELECT "bounds"
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83
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84 architecture ARM
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85 {
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86 endianness
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87 {
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88 little;
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89 big;
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90 }
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91
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92 space linear
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93 {
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94 id = 1;
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95 mau = 8;
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96 map (size = 4G, dest = bus:local_bus);
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97
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98 copytable
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99 (
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100 align = 4,
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101 copy_unit = 1,
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102 dest = linear
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103 );
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104
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105 start_address
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106 (
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107 // It is not strictly necessary to define a run_addr for _START
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108 // because hardware starts execution at address 0x0 which should
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109 // be the vector table with a jump to the relocatable _START, but
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110 // an absolute address can prevent the branch to be out-of-range.
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111 // Or _START may be the entry point at reset and the reset handler
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112 // copies the vector table to address 0x0 after some ROM/RAM memory
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113 // re-mapping. In that case _START should be at a fixed address
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114 // in ROM, specifically the alias of address 0x0 before memory
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115 // re-mapping.
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116 #ifdef __START
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117 run_addr = __START,
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118 #endif
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119 symbol = "_START"
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120 );
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121
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122 stack "stack"
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123 (
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124 #ifdef __STACK_FIXED
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125 fixed,
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126 #endif
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127 align = 4,
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128 min_size = __STACK,
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129 grows = high_to_low
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130 );
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131
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132 heap "heap"
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133 (
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134 #ifdef __HEAP_FIXED
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135 fixed,
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136 #endif
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137 align = 4,
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138 min_size=__HEAP
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139 );
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140
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141 #if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
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142 stack "stack_fiq"
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143 (
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144 fixed,
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145 align = 4,
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146 min_size = __STACK_FIQ,
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147 grows = high_to_low
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148 );
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149 stack "stack_irq"
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150 (
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151 fixed,
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152 align = 4,
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153 min_size = __STACK_IRQ,
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154 grows = high_to_low
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155 );
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156 stack "stack_svc"
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157 (
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158 fixed,
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159 align = 4,
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160 min_size = __STACK_SVC,
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161 grows = high_to_low
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162 );
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163 stack "stack_abt"
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164 (
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165 fixed,
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166 align = 4,
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167 min_size = __STACK_ABT,
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168 grows = high_to_low
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169 );
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170 stack "stack_und"
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171 (
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172 fixed,
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173 align = 4,
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174 min_size = __STACK_UND,
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175 grows = high_to_low
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176 );
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177 #endif
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178
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179 #if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
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180 # if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
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181 // vector table with handler addresses
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182 vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
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183 template = ".text.handler_address",
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184 template_symbol = "_lc_vector_handler",
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185 vector_prefix = "_vector_",
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186 fill = loop,
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187 no_inline
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188 )
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189 {
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190 vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
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191 vector ( id = 1, fill = "_START" );
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192 }
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193 # else
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194 # ifdef __PIC_VECTORS
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195 // vector table with ldrpc instructions from handler table
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196 vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
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197 template = ".text.vector_ldrpc",
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198 template_symbol = "_lc_vector_ldrpc",
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199 vector_prefix = "_vector_ldrpc_",
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200 fill = loop
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201 )
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202 {
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203 }
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204 // subsequent vector table (data pool) with addresses of handlers
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205 vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
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206 template = ".text.handler_address",
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207 template_symbol = "_lc_vector_handler",
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208 vector_prefix = "_vector_",
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209 fill = loop[-32],
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210 no_inline
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211 )
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212 {
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213 vector ( id = 0, fill = "_START" );
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214 }
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215 # else
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216 // vector table with branch instructions to handlers
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217 vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
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218 template = ".text.vector_branch",
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219 template_symbol = "_lc_vector_handler",
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220 vector_prefix = "_vector_",
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221 fill = loop
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222 )
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223 {
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224 vector ( id = 0, fill = "_START" );
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225 }
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226 # endif
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227 # endif
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228 #endif
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229 section_layout
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230 {
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231 #if defined(__NO_AUTO_VECTORS)
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232 "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
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233 "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
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234 #endif
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235 #ifdef __VECTOR_TABLE_RAM_SPACE
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236 // reserve space to copy vector table from ROM to RAM
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237 group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
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238 reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
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239 #endif
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240 #ifdef __VECTOR_TABLE_RAM_COPY
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241 // provide copy address symbols for copy routine
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242 "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
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243 "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
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244 #else
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245 // prevent copy: copy address equals orig address
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246 "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
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247 "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
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248 #endif
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249 // define buffer for string input via Crossview Pro debugger
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250 group ( align = 4 ) reserved "xvwbuffer" (size=__XVWBUF, attributes=rw );
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251
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252 // define labels for bounds begin and end as used in C library
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253 #ifndef BOUNDS_GROUP_REDEFINED
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254 group BOUNDS_GROUP_NAME (ordered, contiguous)
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255 {
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256 select BOUNDS_GROUP_SELECT;
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257 }
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258 #endif
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259 "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
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260 "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
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261
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262 #ifdef __HEAPADDR
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263 group ( ordered, run_addr=__HEAPADDR )
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264 {
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265 select "heap";
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266 }
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diff changeset
267 #endif
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268 #ifdef __STACKADDR
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269 group ( ordered, run_addr=__STACKADDR )
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270 {
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271 select "stack";
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272 }
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273 #endif
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274 #if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
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275 // symbol to set mode bits and interrupt disable bits
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276 // in cstart module before calling the application (main)
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277 "_APPLICATION_MODE_" = __APPLICATION_MODE;
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278 #endif
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279 }
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280 }
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281
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282 bus local_bus
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283 {
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284 mau = 8;
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285 width = 32;
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286 }
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287 }