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annotate libs/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/STM32F10x_XL_Bank1.lsl @ 85:18b154c447bb

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Add note about 1-wire wiring
author Daniel O'Connor <darius@dons.net.au>
date Thu, 12 Mar 2015 23:22:11 +1030
parents c59513fd84fb
children
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1 ////////////////////////////////////////////////////////////////////////////
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2 //
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3 // File : stm32f103_cmsis.lsl
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4 //
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5 // Version : @(#)stm32f103_cmsis.lsl 1.2 09/06/04
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6 //
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7 // Description : LSL file for the STMicroelectronics STM32F103, CMSIS version
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8 //
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9 // Copyright 2009 Altium BV
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10 //
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11 // NOTE:
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12 // This file is derived from cm3.lsl and stm32f103.lsl.
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13 // It is assumed that the user works with the ARMv7M architecture.
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14 // Other architectures will not work with this lsl file.
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15 //
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16 ////////////////////////////////////////////////////////////////////////////
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17
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18 //
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19 // We do not want the vectors as defined in arm_arch.lsl
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20 //
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21 #define __NO_DEFAULT_AUTO_VECTORS 1
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22 #define __NR_OF_VECTORS 76
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23
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24
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25 #ifndef __STACK
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26 # define __STACK 2k
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27 #endif
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28 #ifndef __HEAP
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29 # define __HEAP 2k
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30 #endif
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31 #ifndef __VECTOR_TABLE_ROM_ADDR
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32 # define __VECTOR_TABLE_ROM_ADDR 0x08000000
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33 #endif
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34 #ifndef __XVWBUF
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35 #define __XVWBUF 256 /* buffer used by CrossView */
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36 #endif
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37
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38 #include <arm_arch.lsl>
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39
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40 ////////////////////////////////////////////////////////////////////////////
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41 //
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42 // In the STM32F10x, 3 different boot modes can be selected
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43 // - User Flash memory is selected as boot space
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44 // - SystemMemory is selected as boot space
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45 // - Embedded SRAM is selected as boot space
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46 //
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47 // This aliases the physical memory associated with each boot mode to Block
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48 // 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
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49 // the related memory (Flash memory or SRAM) is still accessible at its
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50 // original memory space.
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51 //
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52 // If no memory is defined yet use the following memory settings
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53 //
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54 #ifndef __MEMORY
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55
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56 memory stm32f103flash
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57 {
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58 mau = 8;
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59 type = rom;
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60 size = 512k;
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61 map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
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62 }
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63
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64 memory stm32f103ram
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65 {
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66 mau = 8;
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67 type = ram;
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68 size = 96k;
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69 map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
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70 }
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71
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72 #endif /* __MEMORY */
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73 section_layout ::linear
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74 {
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75 group( contiguous )
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76 {
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77 select ".bss.stack";
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78 select "stack";
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79 }
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80 }
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81
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82
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83 //
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84 // Custom vector table defines interrupts according to CMSIS standard
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85 //
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86 # if defined(__CPU_ARMV7M__)
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87 section_setup ::linear
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88 {
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89 // vector table with handler addresses
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90 vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
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91 template = ".text.handler_address",
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92 template_symbol = "_lc_vector_handler",
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93 vector_prefix = "_vector_",
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94 fill = loop,
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95 no_inline
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96 )
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97 {
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98 vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
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99 vector ( id = 1, fill = "_START" );
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100 vector ( id = 2, optional, fill = "NMI_Handler" );
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101 vector ( id = 3, optional, fill = "HardFault_Handler" );
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102 vector ( id = 4, optional, fill = "MemManage_Handler" );
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103 vector ( id = 5, optional, fill = "BusFault_Handler" );
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104 vector ( id = 6, optional, fill = "UsageFault_Handler" );
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105 vector ( id = 11, optional, fill = "SVC_Handler" );
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106 vector ( id = 12, optional, fill = "DebugMon_Handler" );
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107 vector ( id = 14, optional, fill = "PendSV_Handler" );
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108 vector ( id = 15, optional, fill = "SysTick_Handler" );
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109
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110 // External Interrupts :
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111 vector ( id = 16, optional, fill = "WWDG_IRQHandler" ); // Window Watchdog
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112 vector ( id = 17, optional, fill = "PVD_IRQHandler" ); // PVD through EXTI Line detect
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113 vector ( id = 18, optional, fill = "TAMPER_IRQHandler" ); // Tamper
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114 vector ( id = 19, optional, fill = "RTC_IRQHandler" ); // RTC
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115 vector ( id = 20, optional, fill = "FLASH_IRQHandler" ); // Flash
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116 vector ( id = 21, optional, fill = "RCC_IRQHandler" ); // RCC
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117 vector ( id = 22, optional, fill = "EXTI0_IRQHandler" ); // EXTI Line 0
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118 vector ( id = 23, optional, fill = "EXTI1_IRQHandler" ); // EXTI Line 1
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119 vector ( id = 24, optional, fill = "EXTI2_IRQHandler" ); // EXTI Line 2
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120 vector ( id = 25, optional, fill = "EXTI3_IRQHandler" ); // EXTI Line 3
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121 vector ( id = 26, optional, fill = "EXTI4_IRQHandler" ); // EXTI Line 4
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122 vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" ); // DMA Channel 1
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123 vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" ); // DMA Channel 2
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124 vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" ); // DMA Channel 3
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125 vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" ); // DMA Channel 4
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126 vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" ); // DMA Channel 5
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127 vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" ); // DMA Channel 6
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128 vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" ); // DMA Channel 7
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129 vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" ); // ADC1 and ADC2
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130 vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" ); // USB High Priority or CAN1 TX
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131 vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" ); // USB LowPriority or CAN1 RX0
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132 vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" ); // CAN1 RX1
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133 vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" ); // CAN1 SCE
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134 vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" ); // EXTI Line 9..5
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135 vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" ); // TIM1 Break
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136 vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" ); // TIM1 Update
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137 vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" ); // TIM1 Trigger and Commutation
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138 vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" ); // TIM1 Capture Compare
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139 vector ( id = 44, optional, fill = "TIM2_IRQHandler" ); // TIM2
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140 vector ( id = 45, optional, fill = "TIM3_IRQHandler" ); // TIM3
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141 vector ( id = 46, optional, fill = "TIM4_IRQHandler" ); // TIM4
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142 vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" ); // I2C1 Event
c59513fd84fb Initial commit of STM32 test code.
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parents:
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143 vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" ); // I2C1 Error
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
144 vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" ); // I2C2 Event
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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145 vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" ); // I2C2 Error
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
146 vector ( id = 51, optional, fill = "SPI1_IRQHandler" ); // SPI1
c59513fd84fb Initial commit of STM32 test code.
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147 vector ( id = 52, optional, fill = "SPI2_IRQHandler" ); // SPI2
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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148 vector ( id = 53, optional, fill = "USART1_IRQHandler" ); // USART1
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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149 vector ( id = 54, optional, fill = "USART2_IRQHandler" ); // USART2
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
150 vector ( id = 55, optional, fill = "USART3_IRQHandler" ); // USART3
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
151 vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" ); // EXTI Line 15..10
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
152 vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" ); // RTC Alarm through EXTI Line
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
153 vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" ); // USB Wakeup from suspend
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
154 vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" ); // TIM8 Break
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
155 vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" ); // TIM8 Update
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
156 vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" ); // TIM8 Trigger and Commutation
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
157 vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" ); // TIM8 Capture Compare
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
158 vector ( id = 63, optional, fill = "ADC3_IRQHandler" ); // ADC3
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
159 vector ( id = 64, optional, fill = "FSMC_IRQHandler" ); // FSMC
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
160 vector ( id = 65, optional, fill = "SDIO_IRQHandler" ); // SDIO
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
161 vector ( id = 66, optional, fill = "TIM5_IRQHandler" ); // TIM5
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
162 vector ( id = 67, optional, fill = "SPI3_IRQHandler" ); // SPI3
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
163 vector ( id = 68, optional, fill = "UART4_IRQHandler" ); // UART4
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
164 vector ( id = 69, optional, fill = "UART5_IRQHandler" ); // UART5
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
165 vector ( id = 70, optional, fill = "TIM6_IRQHandler" ); // TIM6
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
166 vector ( id = 71, optional, fill = "TIM7_IRQHandler" ); // TIM7
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
167 vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" ); // DMA2 Channel1
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
168 vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" ); // DMA2 Channel2
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
169 vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" ); // DMA2 Channel3
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
170 vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" ); // DMA2 Channel4 and DMA2 Channel5
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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171 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
parents:
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172 }
c59513fd84fb Initial commit of STM32 test code.
Daniel O'Connor <darius@dons.net.au>
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173 # endif