*******************************************************************************************************
*
*  GAN041_650WSB Preliminary Spice Model 22/03/2021
*
*  Model generated by Nexperia UK Ltd
*     Copyright(c) 2021
*     All rights reserved
*
*  Contains proprietary information which is the property of Nexperia.
*
*  The information presented in this document is believed to be accurate and 
*  reliable and may be changed without notice. No liability will be accepted by the
*  publisher for any consequence of its use.
*
*  Nexperia UK Ltd
*
*  650V GaN FET Version 2.0
******************************************************************************************************

.subckt GAN041_650WSB 301 302 303 334
*
*  301=D1, 302=G1, 303=S1, 334=mb
*
*
*******************
**  HEMT_A Begin **
* xxxx
* 101=drainHA, 102=gateHA, 103=sourceHA, 106=Si substrate

*bs 109 103 v=0.0005*i(bs) + 50u*i(bs)**2 *rbs 109 103 10

j1 104 102 103 j1mod area=1.09
.model j1mod NJF vto -20 beta 9 lambda 0.01 rs 0.0007
+ cgs 1p cgd 1p is=0.1f

j2 105 102 104 j2mod area=1.09
.model j2mod NJF vto -98 beta 6.5 lambda 0.01
+ cgs 1p cgd 1p is=0.1f

j3 101 102 105 j3mod area=1.09
.model j3mod NJF vto -250 beta 1.7 lambda 0.01 rd {rd_temp}
+ cgs 1p cgd 1p is=0.1f
.param rd_temp=(28.9m+((temp-25)*160u)+(((temp-25)*(temp-25))*1.28u))

CDS 101 103 12pF

bcgs 103 102 i=v(123,0)*i(vcgs)
Ccgs 121 122 0.7E-12
Vcgs 121 0 0Vdc
Ecgs1 122 0 103 102 1
Ecgs2 123 0 TABLE {V(122)}
+ (0,300)
+ (18,100)
+ (33,0)

bcg1 104 102 i=v(133,0)*i(vcg1)
Ccg1 131 132 0.7E-12
Vcg1 131 0 0Vdc
Ecg11 132 0 104 102 1
Ecg12 133 0 TABLE {V(132)}
+ (0,200)
+ (19,200)
+ (40,155)
+ (68,84)
+ (98,0)

bcg2 105 102 i=v(143,0)*i(vcg2)
Ccg2 141 142 1E-12
Vcg2 141 0 0Vdc
Ecg21 142 0 105 102 1
Ecg22 143 0 TABLE {V(142)}
+ (0,159)
+ (98,159)
+ (143,110)
+ (193,45)
+ (250,0)

bcgd 101 102 i=v(148,0)*i(vcgd)
Ccgd 146 147 0.93E-12
Vcgd 146 0 0Vdc
Ecgd1 147 0 101 102 1
Ecgd2 148 0 TABLE {V(147)}
+ (0,110)
+ (250,110)
+ (400,106)
+ (650,97)

cssub 106 103 39pF
bdsub 101 106 i=v(113,0)*i(vdsub)

Cbdsub 111 112 1E-12
Vdsub 111 0 0Vdc
E11 112 0 101 106 1
E12 113 0 TABLE {V(101,102)}
+ (0,127)
+ (19,127)
+ (98,85)
+ (250,62)
+ (600,11)

**  HEMT_A End  **
******************

********************
**  NMOS_A Begin  **
*
* 151a=drainMA, 152=gateMA, 153=sourceMA

XSiMOSFET 151 152 153 FETmod
rsisnub 151 160 10
csisnub 160 153 1p  

**  NMOS_A End  **
******************

******************

****************** 
** Package capacitance and bias resistance  Begin **
*
rbb 103 153 9meg
 
* parasitic Miller capacitance 
CGDA1 321 101 2pF
 
* substrate bonded to paddle of TO-247
rcssub 334 106 0.1  
*GaN gate to substrate
Rgg 102 106 0.1

** Package capacitance and bias resistance  End **
******************

********************************
***   Pin Connection Begin   ***
********************************
**  Wire bonds to source common  **
 
Li1A 103 151 1pH rser=1u
 
* Si source to Source Common
Li3A 199 197 {Li3} rser=1u
RLi3A 199 197 {Rli3}
Ri3A 197 153 0.03  
Li3B 197 193 12p rser=1u
Ri3B 193 153 11m
Li3C 193 192 1p rser=1u
Ri3C 192 153 0.63m
 
********************
**  301=D1 Begin  **
* from 101=drainA to 301=D1
  
L315 301 311 {L31} rser=1u
R315 301 311 {Rl31}
R311 311 101 43m 
L311 311 312 16p rser=1u
R312 312 101 20m 
L312 312 313 40p rser=1u
R313 313 101 1.4m 
 
**  301=D1 End  **
******************
 
********************
**  302=G1 Begin  **
* from 152=GateA to 302=G1
 
L320 302 325 {L32} rser=1u
R320 302 325 {Rl32}
 
r1 325 321 0.1 

R321 321 152 175m 
L321 321 322 101p rser=1u
R322 322 152 80m 
L322 322 323 180p rser=1u
R323 323 152 10.5m 
 
**  302=G1 End  **
******************
 
********************
**  303=S1 Begin  **
* from 199=sourceA to 303=S1
 
 
L335B 303 331 {L33B} rser=1u
R335 303 331 {Rl33B}
R331 331 334 30m 
L331 331 332 16p rser=1u
R332 332 334 11m 
L332 332 333 12p rser=1u
R333 333 334 0.39mm 
L335A  334 199 {L33A} rser=1u ; 
RL335A 334  199 {Rl33A} 
 
**  303=S1 End  **
******************
  
******************************
***   Pin Connection End   ***
******************************

.param Li2=0.6nH rser=1u
.param Rli2=1.13
 
.param Li3=0.33nH rser=1u
.param Rli3=.0207
 
.param L31=5.12nH rser=1u
.param Rl31=0.321
 
.param L32=2nH rser=1u
.param Rl32=0.514
 
.param L33B=1nH rser=1u
.param Rl33B=0.308
.param L33A=0.5nH rser=1u
.param Rl33A=0.0628

.ends GAN041_650WSB

*****************************************************************************************


.SUBCKT FETmod D G S

RLD1 D 4 1.000u
RLS1 S 7 0.2m

Rsnub 3 SN 0.49
Csnub SN 6 0.78n

* Drain,gate and source resistances
RD 4 3 0.1m TC1=7.137m TC2=1.009n
RG G 2 1.6
RS 6 7 1.000u

* Body Diode
RBD 9 4 1u TC1=-5m TC2=0u
DBD 7 9 D_DBD
RDS 7 4 24.00MEG TC1=-5.000m

* Internal MOS
M1 3 2 6 6 MINT

* Gate leakage and gate capacitance
RGS 2 6 4000MEG
CGS 2 6 1.37n

* CGD
C11 11 12 1E-12
V11 11 0 0Vdc
B11 3 2 I= V(13,0)*I(V11)
E11 12 0 3 2 1
E12 13 0 TABLE {V(12)}
+ (-20.0,572.18) 
+ (-16.0,572.18) 
+ (-15.0,572.18) 
+ (-12.0,572.18) 
+ (-10.0,572.18) 
+ (-8.0,572.18) 
+ (-6.0,572.18) 
+ (-5.0,572.18) 
+ (-4.0,572.18) 
+ (-3.0,572.18) 
+ (-2.0,501.12) 
+ (-1.0,405.85) 
+ (-0.5,377.14) 
+ (-0.2,363.27) 
+ (-0.1,363.37) 
+ (0.0,364.3716) 
+ (0.1,355.82) 
+ (0.2,355.89) 
+ (0.5,331.466) 
+ (1.0,298.092) 
+ (2.0,249.957) 
+ (3.0,218.532) 
+ (4.0,195.414) 
+ (5.0,177.109) 
+ (6.0,163.232) 
+ (8.0,145.508) 
+ (10.0,135.726) 
+ (12.0,130.12) 
+ (15.0,125.703)

.param Vto_temp=(5.15-((temp-25)*0.002))

.MODEL MINT NMOS Vto={Vto_temp} Kp=300 Nfs=900G Eta=10000
+ Level=3 Gamma=0.000 Phi= 600.0m Is=1.000E-24 UO=600.0 Js= 0.000 
+ Pb=800.0m Cj=0.000 Cjsw=0.000 Cgso=0.000 Cgdo=0.000 Cgbo=0.000 Tox= 
+ 100.0n Xj 0.000
+ Vmax=400

.MODEL D_DBD D Bv= 33.00 Ibv= 250.0u Rs=1.000u Is=1.061p
+ N=1.000 M=543.8m VJ=960.6m Fc=500.0m Cjo=2.98n Tt=2n

.ENDS FETmod