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Add GAN190-650FBE simulation
author Daniel O'Connor <darius@dons.net.au>
date Mon, 16 Oct 2023 23:20:01 +1030
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1 *ISL55110 Spice Model
2 * Delays now simulated with Delay Lines instead of RC Time Constants
3 * Models
4 *$
5 .model SWOUTN VSWITCH ron=2.83 roff=100Meg von=+.2 voff=-.2
6 *$
7 .model SWOUTP VSWITCH ron=2.6 roff=100Meg von=.2 voff=-.2
8 *$
9 .model den D (n=1)
10 *$
11 .model SWMOD VSWITCH ron=10 roff=100Meg von=+.1 voff=-.1
12 *$
13 .model SWHIZ VSWITCH ron=100Meg roff=0.001 von=+.2 voff=-.2
14 *$
15
16 * Components Definitions
17 *Input PAD
18 .subckt IN_PAD 1 2
19 RIN 1 2 100e6
20 CIN 1 2 1e-12
21 .ends
22 *$
23 * Output PAD (IN GND)
24 .subckt OUT_PAD 1 2
25 RIN 1 2 100e6
26 * CIN should be adjusted depending on the power down time.(PD time - 10 ns )
27 CIN 1 2 14e-12
28 .ends
29 *$
30 *Comparator with hysterisis
31 *COMP_HS IN OUT VDD GND
32 .subckt COMP_HS 1 2 3 4
33 * Thresholds
34 VTHR1 7 4 1.2
35 VTHR2 8 4 1.4
36 * VDD/2 Generation
37 R1 3 9 100e6
38 R2 4 9 100e6
39 *Delayed output
40 R3 2 21 3e3
41 C1 21 4 0.43e-12
42 SW1 7 10 21 9 SWMOD
43 SW2 8 10 9 21 SWMOD
44 *COMPARISON
45 SW3 3 2 1 10 SWMOD
46 SW4 4 2 10 1 SWMOD
47 .ends
48 *$
49 * Buffer Models ( IN OUT VDD GND)
50 .subckt BUF_X 1 2 3 4
51 *Generating VDD/2
52 R1 3 7 100e6
53 R2 4 7 100e6
54 SW1 3 2 1 7 SWMOD
55 SW2 4 2 7 1 SWMOD
56 .ends
57 *$
58 *Level shifter (IN OUT LV_SUPPLY GND HV_SUPPLY)
59 .subckt LS 1 2 3 4 5
60 *Gnerating VDD/2
61 R1 3 7 100e6
62 R2 4 7 100e6
63 SW1 5 2 1 7 SWMOD
64 SW2 4 2 7 1 SWMOD
65 .ends
66 *$
67 * Delay from LV(VDD) components in signal path
68 * LV comparator and level shifter give a delay of 3 ns(approx).
69 * T=0.69*R*C Obsolete, use delay line model instead
70 * Delay_LV IN OUT GND
71 .subckt Delay_LV 1 2 3
72 T1 1 3 2 3 Z0=100Meg TD=3n
73 R1 2 3 100Meg
74 *C1 2 3 0.43e-12
75 .ends
76 *$
77 * Delay from HV inverters in the signal path.
78 * though this delay vary with supply(VH) , modeled delay as 6 ns .
79 * T=0.69*R*C Obsolete, use delay line model instead
80 .subckt Delay_HV 1 2 3
81 T1 1 3 2 3 Z0=100Meg TD=6n
82 R1 2 3 100Meg
83 *C1 2 3 0.43e-12
84 .ends
85
86 *$
87 .subckt DelaY_HV-1 1 2 3
88 T1 1 3 2 3 Z0=100Meg TD=3n
89 R1 2 3 100Meg
90 *C1 2 3 0.43e-12
91 .ends
92 *$
93 *ISL55110 model
94 *
95 * VDD PD IN_B IN_A OA VH GND OB ENABLEZ
96 * | | | | | | | | |
97 * | | | | | | | | |
98 * | | | | | | | | |
99 * | | | | | | | | |
100 * | | | | | | | | |
101 * | | | | | | | | |
102 * | | | | | | | | |
103 * | | | | | | | | |
104 * | | | | | | | | |
105 * | | | | | | | | |
106 * | | | | | | | | |
107 * | | | | | | | | |
108 .subckt ISL55110 1 2 3 4 5 6 7 8 9
109 XPAD_INB 3 7 IN_PAD
110 XPAD_INA 4 7 IN_PAD
111 XPAD_PD 2 7 IN_PAD
112 XPAD_ENZ 9 7 IN_PAD
113 *Input Clamp Diodes for IBIS
114 d5 7 3 den
115 d6 3 1 den
116 d7 7 4 den
117 d8 4 1 den
118 d9 7 2 den
119 d10 2 1 den
120 d11 7 9 den
121 d12 9 1 den
122 *
123 *
124 *
125 R1 1 99 100e6
126 R2 99 7 100e6
127 R10 6 199 100e6
128 R11 7 199 100e6
129 XCOMP_A 4 10 1 7 COMP_HS
130 XCOMP_B 3 11 1 7 COMP_HS
131 XDELAY_LVA 10 12 7 Delay_LV
132 XDELAY_LVB 11 13 7 Delay_LV
133 XLEVEL_SHIFTERA 12 14 1 7 6 LS
134 XLEVEL_SHIFTERB 13 15 1 7 6 LS
135 XDELAY_HVA 14 16 7 Delay_HV
136 XDELAY_HVB 15 17 7 Delay_HV
137 *PD or ENABLEZ
138 R3 18 7 100e6
139 SW1 1 18 2 99 SWMOD
140 *SW2 1 18 9 99 SWMOD
141 SWA 16 19 99 18 SWMOD
142 SWB 17 20 99 18 SWMOD
143 V 210 7 -1
144 R4 19 210 100e6
145 R5 20 210 100e6
146 * OUTPUT SWITCHES
147 *OA Switch
148 T1 9 7 230 7 Z0=100Meg TD=15n
149 R6 230 7 100Meg
150 SWTPA 6 220 230 99 SWHIZ
151 *
152 SWPA 220 5 19 199 SWOUTP
153 SWNA 221 5 199 19 SWOUTN
154 *
155 SWTNA 7 221 230 99 SWHIZ
156 *
157 C1 5 7 100pF
158 d1 7 5 den
159 d2 5 6 den
160 XPAD_OUTA 5 7 OUT_PAD
161 *
162 *
163 * OB Switch
164 *HIZ High Side
165 SWTPB 6 222 230 99 SWHIZ
166 *
167 SWPB 222 8 20 199 SWOUTP
168 SWNB 223 8 199 20 SWOUTN
169 *HIX Low Side
170 SWTNB 7 223 230 99 SWHIZ
171 C2 8 7 100pF
172 d3 7 8 den
173 d4 8 6 den
174 XPAD_OUTB 8 7 OUT_PAD
175 .ends
176
177 *$