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annotate isl55110.lib @ 16:1c4ff82b5704

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Tweak values
author Daniel O'Connor <darius@dons.net.au>
date Sun, 19 Nov 2023 17:36:45 +1030
parents 22c97f9ed2cc
children
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22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
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1 *ISL55110 Spice Model
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Daniel O'Connor <darius@dons.net.au>
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2 * Delays now simulated with Delay Lines instead of RC Time Constants
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3 * Models
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4 *$
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5 .model SWOUTN VSWITCH ron=2.83 roff=100Meg von=+.2 voff=-.2
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6 *$
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7 .model SWOUTP VSWITCH ron=2.6 roff=100Meg von=.2 voff=-.2
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8 *$
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9 .model den D (n=1)
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10 *$
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11 .model SWMOD VSWITCH ron=10 roff=100Meg von=+.1 voff=-.1
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12 *$
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13 .model SWHIZ VSWITCH ron=100Meg roff=0.001 von=+.2 voff=-.2
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14 *$
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15
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16 * Components Definitions
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17 *Input PAD
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Daniel O'Connor <darius@dons.net.au>
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18 .subckt IN_PAD 1 2
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Daniel O'Connor <darius@dons.net.au>
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19 RIN 1 2 100e6
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Daniel O'Connor <darius@dons.net.au>
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20 CIN 1 2 1e-12
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21 .ends
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22 *$
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Daniel O'Connor <darius@dons.net.au>
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23 * Output PAD (IN GND)
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24 .subckt OUT_PAD 1 2
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25 RIN 1 2 100e6
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26 * CIN should be adjusted depending on the power down time.(PD time - 10 ns )
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27 CIN 1 2 14e-12
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28 .ends
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29 *$
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Daniel O'Connor <darius@dons.net.au>
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30 *Comparator with hysterisis
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Daniel O'Connor <darius@dons.net.au>
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31 *COMP_HS IN OUT VDD GND
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Daniel O'Connor <darius@dons.net.au>
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32 .subckt COMP_HS 1 2 3 4
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Daniel O'Connor <darius@dons.net.au>
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33 * Thresholds
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Daniel O'Connor <darius@dons.net.au>
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34 VTHR1 7 4 1.2
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35 VTHR2 8 4 1.4
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Daniel O'Connor <darius@dons.net.au>
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36 * VDD/2 Generation
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37 R1 3 9 100e6
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38 R2 4 9 100e6
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39 *Delayed output
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40 R3 2 21 3e3
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41 C1 21 4 0.43e-12
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42 SW1 7 10 21 9 SWMOD
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43 SW2 8 10 9 21 SWMOD
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Daniel O'Connor <darius@dons.net.au>
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44 *COMPARISON
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45 SW3 3 2 1 10 SWMOD
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46 SW4 4 2 10 1 SWMOD
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47 .ends
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Daniel O'Connor <darius@dons.net.au>
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48 *$
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Daniel O'Connor <darius@dons.net.au>
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49 * Buffer Models ( IN OUT VDD GND)
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Daniel O'Connor <darius@dons.net.au>
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50 .subckt BUF_X 1 2 3 4
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Daniel O'Connor <darius@dons.net.au>
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51 *Generating VDD/2
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Daniel O'Connor <darius@dons.net.au>
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52 R1 3 7 100e6
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Daniel O'Connor <darius@dons.net.au>
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53 R2 4 7 100e6
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Daniel O'Connor <darius@dons.net.au>
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54 SW1 3 2 1 7 SWMOD
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55 SW2 4 2 7 1 SWMOD
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56 .ends
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57 *$
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Daniel O'Connor <darius@dons.net.au>
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58 *Level shifter (IN OUT LV_SUPPLY GND HV_SUPPLY)
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Daniel O'Connor <darius@dons.net.au>
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59 .subckt LS 1 2 3 4 5
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Daniel O'Connor <darius@dons.net.au>
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60 *Gnerating VDD/2
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Daniel O'Connor <darius@dons.net.au>
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61 R1 3 7 100e6
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Daniel O'Connor <darius@dons.net.au>
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62 R2 4 7 100e6
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Daniel O'Connor <darius@dons.net.au>
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63 SW1 5 2 1 7 SWMOD
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64 SW2 4 2 7 1 SWMOD
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65 .ends
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66 *$
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Daniel O'Connor <darius@dons.net.au>
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67 * Delay from LV(VDD) components in signal path
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68 * LV comparator and level shifter give a delay of 3 ns(approx).
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69 * T=0.69*R*C Obsolete, use delay line model instead
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70 * Delay_LV IN OUT GND
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Daniel O'Connor <darius@dons.net.au>
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71 .subckt Delay_LV 1 2 3
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Daniel O'Connor <darius@dons.net.au>
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72 T1 1 3 2 3 Z0=100Meg TD=3n
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73 R1 2 3 100Meg
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74 *C1 2 3 0.43e-12
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75 .ends
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76 *$
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Daniel O'Connor <darius@dons.net.au>
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77 * Delay from HV inverters in the signal path.
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Daniel O'Connor <darius@dons.net.au>
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78 * though this delay vary with supply(VH) , modeled delay as 6 ns .
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79 * T=0.69*R*C Obsolete, use delay line model instead
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Daniel O'Connor <darius@dons.net.au>
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80 .subckt Delay_HV 1 2 3
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Daniel O'Connor <darius@dons.net.au>
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81 T1 1 3 2 3 Z0=100Meg TD=6n
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82 R1 2 3 100Meg
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83 *C1 2 3 0.43e-12
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84 .ends
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85
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86 *$
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87 .subckt DelaY_HV-1 1 2 3
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Daniel O'Connor <darius@dons.net.au>
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88 T1 1 3 2 3 Z0=100Meg TD=3n
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89 R1 2 3 100Meg
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90 *C1 2 3 0.43e-12
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91 .ends
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92 *$
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Daniel O'Connor <darius@dons.net.au>
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93 *ISL55110 model
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Daniel O'Connor <darius@dons.net.au>
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94 *
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95 * VDD PD IN_B IN_A OA VH GND OB ENABLEZ
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96 * | | | | | | | | |
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97 * | | | | | | | | |
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98 * | | | | | | | | |
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99 * | | | | | | | | |
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100 * | | | | | | | | |
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101 * | | | | | | | | |
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102 * | | | | | | | | |
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103 * | | | | | | | | |
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104 * | | | | | | | | |
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105 * | | | | | | | | |
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106 * | | | | | | | | |
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107 * | | | | | | | | |
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108 .subckt ISL55110 1 2 3 4 5 6 7 8 9
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109 XPAD_INB 3 7 IN_PAD
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110 XPAD_INA 4 7 IN_PAD
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Daniel O'Connor <darius@dons.net.au>
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111 XPAD_PD 2 7 IN_PAD
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Daniel O'Connor <darius@dons.net.au>
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112 XPAD_ENZ 9 7 IN_PAD
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Daniel O'Connor <darius@dons.net.au>
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113 *Input Clamp Diodes for IBIS
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114 d5 7 3 den
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115 d6 3 1 den
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116 d7 7 4 den
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Daniel O'Connor <darius@dons.net.au>
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117 d8 4 1 den
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Daniel O'Connor <darius@dons.net.au>
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118 d9 7 2 den
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Daniel O'Connor <darius@dons.net.au>
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119 d10 2 1 den
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Daniel O'Connor <darius@dons.net.au>
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120 d11 7 9 den
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Daniel O'Connor <darius@dons.net.au>
parents:
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121 d12 9 1 den
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Daniel O'Connor <darius@dons.net.au>
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122 *
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Daniel O'Connor <darius@dons.net.au>
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123 *
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Daniel O'Connor <darius@dons.net.au>
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124 *
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Daniel O'Connor <darius@dons.net.au>
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125 R1 1 99 100e6
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Daniel O'Connor <darius@dons.net.au>
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126 R2 99 7 100e6
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Daniel O'Connor <darius@dons.net.au>
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127 R10 6 199 100e6
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Daniel O'Connor <darius@dons.net.au>
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128 R11 7 199 100e6
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Daniel O'Connor <darius@dons.net.au>
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129 XCOMP_A 4 10 1 7 COMP_HS
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Daniel O'Connor <darius@dons.net.au>
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130 XCOMP_B 3 11 1 7 COMP_HS
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Daniel O'Connor <darius@dons.net.au>
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131 XDELAY_LVA 10 12 7 Delay_LV
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Daniel O'Connor <darius@dons.net.au>
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132 XDELAY_LVB 11 13 7 Delay_LV
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Daniel O'Connor <darius@dons.net.au>
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133 XLEVEL_SHIFTERA 12 14 1 7 6 LS
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Daniel O'Connor <darius@dons.net.au>
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134 XLEVEL_SHIFTERB 13 15 1 7 6 LS
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Daniel O'Connor <darius@dons.net.au>
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135 XDELAY_HVA 14 16 7 Delay_HV
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Daniel O'Connor <darius@dons.net.au>
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136 XDELAY_HVB 15 17 7 Delay_HV
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Daniel O'Connor <darius@dons.net.au>
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137 *PD or ENABLEZ
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Daniel O'Connor <darius@dons.net.au>
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138 R3 18 7 100e6
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Daniel O'Connor <darius@dons.net.au>
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139 SW1 1 18 2 99 SWMOD
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Daniel O'Connor <darius@dons.net.au>
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140 *SW2 1 18 9 99 SWMOD
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Daniel O'Connor <darius@dons.net.au>
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141 SWA 16 19 99 18 SWMOD
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Daniel O'Connor <darius@dons.net.au>
parents:
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142 SWB 17 20 99 18 SWMOD
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Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
143 V 210 7 -1
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
144 R4 19 210 100e6
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
145 R5 20 210 100e6
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
146 * OUTPUT SWITCHES
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
147 *OA Switch
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Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
148 T1 9 7 230 7 Z0=100Meg TD=15n
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
149 R6 230 7 100Meg
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
150 SWTPA 6 220 230 99 SWHIZ
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
151 *
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
152 SWPA 220 5 19 199 SWOUTP
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
153 SWNA 221 5 199 19 SWOUTN
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
154 *
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
155 SWTNA 7 221 230 99 SWHIZ
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
156 *
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
157 C1 5 7 100pF
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
158 d1 7 5 den
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
159 d2 5 6 den
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
160 XPAD_OUTA 5 7 OUT_PAD
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
161 *
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
162 *
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
163 * OB Switch
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Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
164 *HIZ High Side
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
165 SWTPB 6 222 230 99 SWHIZ
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
166 *
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
167 SWPB 222 8 20 199 SWOUTP
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
168 SWNB 223 8 199 20 SWOUTN
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
169 *HIX Low Side
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
170 SWTNB 7 223 230 99 SWHIZ
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
171 C2 8 7 100pF
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
172 d3 7 8 den
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
173 d4 8 6 den
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
174 XPAD_OUTB 8 7 OUT_PAD
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
175 .ends
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
176
22c97f9ed2cc Add GAN190-650FBE simulation
Daniel O'Connor <darius@dons.net.au>
parents:
diff changeset
177 *$