| Thu, 27 Feb 2025 13:58:37 +1030 |
Daniel O'Connor |
Use 8 bit auto pull otherwise the PIOs jitter (due to DMA contention I guess?)
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| Wed, 26 Feb 2025 11:03:59 +1030 |
Daniel O'Connor |
Run PIOs at 1x with delays and sync.
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| Tue, 25 Feb 2025 17:03:51 +1030 |
Daniel O'Connor |
Add comment
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| Tue, 25 Feb 2025 16:53:32 +1030 |
Daniel O'Connor |
Cascade IRQs from DAC to control so manual & external trigger are the same.
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| Tue, 25 Feb 2025 16:47:00 +1030 |
Daniel O'Connor |
Add sideset for trigger output.
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| Tue, 25 Feb 2025 15:56:49 +1030 |
Daniel O'Connor |
Remove debug prints and #ifdef now the control code works.
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| Tue, 25 Feb 2025 15:46:03 +1030 |
Daniel O'Connor |
Don't mark pulse active on slew up/down.
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| Tue, 25 Feb 2025 14:53:40 +1030 |
Daniel O'Connor |
Set control data after shape data so it is lined up properly.
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| Tue, 25 Feb 2025 14:36:10 +1030 |
Daniel O'Connor |
WIP with control and DAC in sync and not hanging.
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| Tue, 25 Feb 2025 13:40:57 +1030 |
Daniel O'Connor |
Move SM reset & DMA reprogramming to DMA IRQ handler, only trigger in PWM IRQ handler.
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| Tue, 25 Feb 2025 13:31:27 +1030 |
Daniel O'Connor |
Commit WIP ctrl code
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| Mon, 24 Feb 2025 15:58:57 +1030 |
Daniel O'Connor |
Use PWM output to feed PIO trigger
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| Mon, 24 Feb 2025 12:12:09 +1030 |
Daniel O'Connor |
Reset DAC PIO and use force trigger to do manual trigger.
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| Fri, 21 Feb 2025 17:27:22 +1030 |
Daniel O'Connor |
Make it actually work
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| Sun, 16 Feb 2025 14:36:33 +1030 |
Daniel O'Connor |
Use interpolator to compute pulse up.
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| Sun, 16 Feb 2025 10:09:05 +1030 |
Daniel O'Connor |
Copy pulse up in reverse for pulse down.
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| Sun, 16 Feb 2025 09:47:44 +1030 |
Daniel O'Connor |
WIP
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| Sat, 15 Feb 2025 22:57:18 +1030 |
Daniel O'Connor |
WIP
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| Mon, 29 Mar 2021 18:05:05 +1030 |
Daniel O'Connor |
DMA test data repeatedly into PIO FIFO
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| Mon, 29 Mar 2021 17:39:00 +1030 |
Daniel O'Connor |
Actually get data moving out.
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| Mon, 29 Mar 2021 13:48:34 +1030 |
Daniel O'Connor |
First commit of code that compiles.
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