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DMA test data repeatedly into PIO FIFO
author Daniel O'Connor <darius@dons.net.au>
date Mon, 29 Mar 2021 18:05:05 +1030
parents 0d653f60dec8
children 2db42eaba3c8
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2:0d653f60dec8 3:b10097c3383d
17 ** 17 **
18 */ 18 */
19 19
20 #include "pico/stdlib.h" 20 #include "pico/stdlib.h"
21 #include "hardware/clocks.h" 21 #include "hardware/clocks.h"
22 #include "hardware/dma.h"
23 #include "hardware/irq.h"
22 #include "hardware/pio.h" 24 #include "hardware/pio.h"
23 25
24 #include "dac.pio.h" 26 #include "dac.pio.h"
25 27
26 #if 0 28 #if 0
31 extern void* sgauss_dat_start; 33 extern void* sgauss_dat_start;
32 #endif 34 #endif
33 35
34 uint8_t shaped_trap_dat_start[] = { 0, 1, 2, 4, 8, 16, 32, 64, 128, 0, 0, 0, 0, 0, 0, 0 }; 36 uint8_t shaped_trap_dat_start[] = { 0, 1, 2, 4, 8, 16, 32, 64, 128, 0, 0, 0, 0, 0, 0, 0 };
35 //uint8_t shaped_trap_dat_start[] = { 0, 1, 2, 3, 1, 2, 0, 3, 1, 1, 2, 3, 0, 1, 2, 3 }; 37 //uint8_t shaped_trap_dat_start[] = { 0, 1, 2, 3, 1, 2, 0, 3, 1, 1, 2, 3, 0, 1, 2, 3 };
38 #define SHAPED_TRAP_DAT_BITS 4
39 _Static_assert((1 << SHAPED_TRAP_DAT_BITS) == sizeof(shaped_trap_dat_start));
40
41 static int dma_chan;
42
43 void
44 dma_handler(void) {
45 // Clear the interrupt request.
46 dma_hw->ints0 = 1u << dma_chan;
47 // Give the channel a new wave table entry to read from, and re-trigger it
48 dma_channel_set_read_addr(dma_chan, shaped_trap_dat_start, true);
49 }
36 50
37 int 51 int
38 main() { 52 main(void) {
39 int i; 53 int i;
40 const uint LED_PIN = PICO_DEFAULT_LED_PIN; 54 const uint LED_PIN = PICO_DEFAULT_LED_PIN;
41 55
42 stdio_init_all(); 56 stdio_init_all();
43 57
51 uint sm = pio_claim_unused_sm(pio, true); 65 uint sm = pio_claim_unused_sm(pio, true);
52 // XXX: I would prefer starting at GPIO16 but in that case the top 2 66 // XXX: I would prefer starting at GPIO16 but in that case the top 2
53 // bits don't seem to work 67 // bits don't seem to work
54 dac_program_init(pio, sm, offset, 14); 68 dac_program_init(pio, sm, offset, 14);
55 69
70 // Configure a channel to write the same word (32 bits) repeatedly to PIO0
71 // SM0's TX FIFO, paced by the data request signal from that peripheral.
72 dma_chan = dma_claim_unused_channel(true);
73 dma_channel_config dmac = dma_channel_get_default_config(dma_chan);
74 channel_config_set_transfer_data_size(&dmac, DMA_SIZE_32);
75 channel_config_set_read_increment(&dmac, true);
76 channel_config_set_ring(&dmac, false, SHAPED_TRAP_DAT_BITS);
77 channel_config_set_dreq(&dmac, DREQ_PIO0_TX0);
78
79 dma_channel_configure(
80 dma_chan,
81 &dmac,
82 &pio0_hw->txf[0], // Write address (only need to set this once)
83 NULL, // Don't provide a read address yet
84 100, // Write this many times then interrupt
85 false // Don't start yet
86 );
87
88 // Tell the DMA to raise IRQ line 0 when the channel finishes a block
89 dma_channel_set_irq0_enabled(dma_chan, true);
90
91 // Configure the processor to run dma_handler() when DMA IRQ 0 is asserted
92 irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
93 irq_set_enabled(DMA_IRQ_0, true);
94
95 // Manually call the handler once, to trigger the first transfer
96 dma_handler();
97
98 // Everything else from this point is interrupt-driven. The processor has
99 // time to sit and think about its early retirement -- maybe open a bakery?
56 while (true) { 100 while (true) {
101 #if 0
57 for (int i = 0; i < sizeof(shaped_trap_dat_start) / 4; i++) { 102 for (int i = 0; i < sizeof(shaped_trap_dat_start) / 4; i++) {
58 pio_sm_put_blocking(pio, sm, ((uint32_t *)shaped_trap_dat_start)[i]); 103 pio_sm_put_blocking(pio, sm, ((uint32_t *)shaped_trap_dat_start)[i]);
59 } 104 }
105 #endif
60 #if 0 106 #if 0
61 gpio_put(LED_PIN, 1); 107 gpio_put(LED_PIN, 1);
62 sleep_ms(100); 108 sleep_ms(100);
63 gpio_put(LED_PIN, 0); 109 gpio_put(LED_PIN, 0);
64 #endif 110 #endif