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Remove debug prints and #ifdef now the control code works.
author Daniel O'Connor <darius@dons.net.au>
date Tue, 25 Feb 2025 15:56:49 +1030
parents 6aaa9658df1e
children c7845db23ab2
comparison
equal deleted inserted replaced
22:9ad0dd5c638c 23:3c713073dd0c
14 ** MODULATOR.C 14 ** MODULATOR.C
15 ** 15 **
16 ** Create modulation shape 16 ** Create modulation shape
17 ** 17 **
18 */ 18 */
19 #define WITH_CTRL
20 //#define WITH_TRIGGER 19 //#define WITH_TRIGGER
21 20
22 #include <stdio.h> 21 #include <stdio.h>
23 #include <string.h> 22 #include <string.h>
24 23
78 static int dac_dma_chan; 77 static int dac_dma_chan;
79 // DAC SM 78 // DAC SM
80 uint dac_sm; 79 uint dac_sm;
81 // Instruction offset for DAC PIO program 80 // Instruction offset for DAC PIO program
82 uint dac_pio_sm_offset; 81 uint dac_pio_sm_offset;
83 #ifdef WITH_CTRL 82
84 // DMA channel to feed ctrl PIO 83 // DMA channel to feed ctrl PIO
85 static int ctrl_dma_chan; 84 static int ctrl_dma_chan;
86 // Ctrl SM 85 // Ctrl SM
87 uint ctrl_sm; 86 uint ctrl_sm;
88 // Instruction offset for ctrl PIO program 87 // Instruction offset for ctrl PIO program
89 uint ctrl_pio_sm_offset; 88 uint ctrl_pio_sm_offset;
90 #endif
91 89
92 /* 90 /*
93 * Use a DMA channel to feed PIO0 SM0 with pulse data. 91 * Use a DMA channel to feed PIO0 SM0 with pulse data.
94 * Each DMA transfer is a single pulse. 92 * Each DMA transfer is a single pulse.
95 * 93 *
100 * pulse (or not if it should stop). ie reset the PIO state machine 98 * pulse (or not if it should stop). ie reset the PIO state machine
101 * back to waiting for an edge and re-arm the DMA. 99 * back to waiting for an edge and re-arm the DMA.
102 */ 100 */
103 void 101 void
104 dma_handler(void) { 102 dma_handler(void) {
105 printf("dma_handler %d\n", get_core_num());
106 // Clear the interrupt request. 103 // Clear the interrupt request.
107 dma_hw->ints0 = 1u << dac_dma_chan; 104 dma_hw->ints0 = 1u << dac_dma_chan;
108 105
106 #if 0
109 printf("DAC transfers %lu\n", dma_channel_hw_addr(dac_dma_chan)->transfer_count); 107 printf("DAC transfers %lu\n", dma_channel_hw_addr(dac_dma_chan)->transfer_count);
110 #ifdef WITH_CTRL
111 printf("Ctrl transfers %lu\n", dma_channel_hw_addr(ctrl_dma_chan)->transfer_count); 108 printf("Ctrl transfers %lu\n", dma_channel_hw_addr(ctrl_dma_chan)->transfer_count);
112 #endif 109 #endif
113 110
114 // Reset DAQ & ctrl PIO SMs so they are waiting for a trigger 111 // Reset DAQ & ctrl PIO SMs so they are waiting for a trigger
115 pio_sm_exec(pulse_pio, dac_sm, pio_encode_jmp(dac_pio_sm_offset)); 112 pio_sm_exec(pulse_pio, dac_sm, pio_encode_jmp(dac_pio_sm_offset));
116 #ifdef WITH_CTRL
117 pio_sm_exec(pulse_pio, ctrl_sm, pio_encode_jmp(ctrl_pio_sm_offset)); 113 pio_sm_exec(pulse_pio, ctrl_sm, pio_encode_jmp(ctrl_pio_sm_offset));
118 #endif
119 114
120 // Setup next pulse data & ctrl DMA addresses 115 // Setup next pulse data & ctrl DMA addresses
121 dma_channel_wait_for_finish_blocking(dac_dma_chan); 116 dma_channel_wait_for_finish_blocking(dac_dma_chan);
122 dma_channel_set_read_addr(dac_dma_chan, pulse_data, true); 117 dma_channel_set_read_addr(dac_dma_chan, pulse_data, true);
123 #ifdef WITH_CTRL
124 dma_channel_wait_for_finish_blocking(ctrl_dma_chan); 118 dma_channel_wait_for_finish_blocking(ctrl_dma_chan);
125 dma_channel_set_read_addr(ctrl_dma_chan, pulse_ctrl, true); 119 dma_channel_set_read_addr(ctrl_dma_chan, pulse_ctrl, true);
126 #endif
127 } 120 }
128 121
129 122
130 void 123 void
131 pwm_wrap(void) { 124 pwm_wrap(void) {
132 printf("pwm_wrap %d\n", get_core_num());
133 pwm_clear_irq(slice_num); 125 pwm_clear_irq(slice_num);
134 126
135 #ifndef WITH_TRIGGER 127 #ifndef WITH_TRIGGER
136 // Manually trigger DAQ SM (cleared by SM) 128 // Manually trigger DAQ SM (cleared by SM)
137 pulse_pio->irq_force = 3; 129 pulse_pio->irq_force = 3;
138 #endif
139 130
140 // 'scope trigger 131 // 'scope trigger
141 gpio_put(2, 1); 132 gpio_put(2, 1);
142 gpio_put(2, 0); 133 gpio_put(2, 0);
134 #endif
143 } 135 }
144 136
145 // Calculate pulse shape data 137 // Calculate pulse shape data
146 // TODO: predistortion, proper sense, gate, phase, active, T/R switch 138 // TODO: predistortion, proper sense, gate, phase, active, T/R switch
147 // Could encode them as bit stream like data but more compact would be 139 // Could encode them as bit stream like data but more compact would be
393 385
394 // Configure the processor to run dma_handler() when DMA IRQ 0 is asserted 386 // Configure the processor to run dma_handler() when DMA IRQ 0 is asserted
395 irq_set_exclusive_handler(DMA_IRQ_0, dma_handler); 387 irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
396 irq_set_enabled(DMA_IRQ_0, true); 388 irq_set_enabled(DMA_IRQ_0, true);
397 389
398 #ifdef WITH_CTRL
399 // Load the ctrl program, and configure a free state machine 390 // Load the ctrl program, and configure a free state machine
400 // to run the program. 391 // to run the program.
401 ctrl_pio_sm_offset = pio_add_program(pulse_pio, &ctrl_program); 392 ctrl_pio_sm_offset = pio_add_program(pulse_pio, &ctrl_program);
402 if (ctrl_pio_sm_offset < 0) { 393 if (ctrl_pio_sm_offset < 0) {
403 printf("Unable to load ctrl program\n"); 394 printf("Unable to load ctrl program\n");
421 pulse_ctrl, // Ctrl data 412 pulse_ctrl, // Ctrl data
422 transfers, // Transfer count 413 transfers, // Transfer count
423 true // Start transfer 414 true // Start transfer
424 ); 415 );
425 // No IRQ, piggyback on the data one 416 // No IRQ, piggyback on the data one
426 #endif
427 417
428 #ifdef WITH_TRIGGER 418 #ifdef WITH_TRIGGER
429 // Load the trigger program, and configure a free state machine 419 // Load the trigger program, and configure a free state machine
430 // to run the program. 420 // to run the program.
431 uint trigger_pio_sm_offset = pio_add_program(pulse_pio, &trigger_program); 421 uint trigger_pio_sm_offset = pio_add_program(pulse_pio, &trigger_program);