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annotate modulator.c @ 7:4ad473648949

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Copy pulse up in reverse for pulse down. Copy first pulse for subsequent pulses.
author Daniel O'Connor <darius@dons.net.au>
date Sun, 16 Feb 2025 10:09:05 +1030
parents 5bed069f0c33
children 0249d0cecac4
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1 /******************************************************************
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2 *******************************************************************
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3 **
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4 ** This is proprietary unpublished source code, property
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5 ** of Genesis Software. Use or disclosure without prior
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6 ** agreement is expressly prohibited.
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7 **
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8 ** Copyright (c) 2021 Genesis Software, all rights reserved.
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9 **
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10 *******************************************************************
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11 ******************************************************************/
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13 /*
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14 ** MODULATOR.C
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15 **
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16 ** Create modulation shape
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17 **
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18 */
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19
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20 #include <stdio.h>
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21 #include <string.h>
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22 #include "bitstring.h"
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23
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24 #pragma GCC diagnostic push
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25 #pragma GCC diagnostic ignored "-Wtype-limits"
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26 #pragma GCC diagnostic ignored "-Wsign-compare"
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27 #include "pico/stdlib.h"
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28 #include "hardware/clocks.h"
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29 #include "hardware/dma.h"
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30 #include "hardware/interp.h"
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31 #include "hardware/irq.h"
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32 #include "hardware/pll.h"
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33 #include "hardware/pio.h"
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34 #include "hardware/pwm.h"
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35 #include "hardware/structs/pll.h"
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36 #include "hardware/structs/clocks.h"
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37 #pragma GCC diagnostic pop
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39 #include "dac.pio.h"
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40
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41 // https://github.com/howerj/q
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42 // Modified to be Q20.12 rather than Q16.16
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43 #include "q/q.h"
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44
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45 #include "shaped-trap.h"
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46
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47 static int dma_chan;
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48 uint8_t pulse_data[65536];
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49 uint8_t pulse_ctrl[65536];
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50
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51 void
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52 dma_handler(void) {
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53 // Clear the interrupt request.
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54 dma_hw->ints0 = 1u << dma_chan;
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55 // Give the channel a new wave table entry to read from, and re-trigger it
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56 //dma_channel_set_read_addr(dma_chan, shaped_trap_dat_start, true);
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57 }
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58
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59 unsigned slice_num = 0;
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60
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61 void
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62 pwm_wrap(void) {
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63 pwm_clear_irq(slice_num);
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64 #if 0
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65 static unsigned state = 0;
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66
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67 gpio_put(PICO_DEFAULT_LED_PIN, state);
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68 state = !state;
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69 #endif
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70
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71 // Trigger another pulse read out
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72 dma_channel_set_read_addr(dma_chan, pulse_data, true);
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73 }
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74
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75 // Calculate pulse shape data
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76 // TODO: sense, gate, phase, active, T/R switch
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77 // Could encode them as bit stream like data but more compact would be
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78 // (say) a list of counts to toggle pins at
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79 #define SENSE 0x01
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80 #define GATE 0x02
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81 #define PHINV 0x04
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82 #define PACTIVE 0x08
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83
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84 // Need to add pre/postgate/sense/phase counters
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85 unsigned
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86 compute_pulse(uint8_t *data, uint8_t *ctrl, unsigned datalen, uint16_t plen, char *code, uint8_t ncode, const uint8_t *shape, uint8_t shapelen, uint8_t codegap, uint8_t slew1, uint8_t slew2, uint8_t dcofs) {
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87 uint32_t shapesamples, nsamples, idx, bit1startup, bit1stopup;
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88 q_t dcscale, stepsize;
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89 char tmps[20];
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90 interp_config cfg;
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91
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92 // Setup lane 0 to generate index into shape table
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93 // Mask start is 0 because we use 8 bit samples
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94 cfg = interp_default_config();
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95 interp_config_set_shift(&cfg, QBITS);
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96 interp_config_set_mask(&cfg, 0, 32 - QBITS);
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97 interp_config_set_blend(&cfg, true);
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98 interp_set_config(interp0, 0, &cfg);
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99
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100 // Setup lane 1 to LERP each sample pair
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101 cfg = interp_default_config();
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102 interp_config_set_shift(&cfg, QBITS - 8);
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103 interp_config_set_signed(&cfg, false);
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104 interp_config_set_cross_input(&cfg, true); // unsigned blending
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105 interp_set_config(interp0, 1, &cfg);
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106
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107 interp0->accum[0] = 0; // Initial offset into shape table
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108 interp0->base[2] = (uintptr_t)shape; // Start of shape table
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109
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110 dcscale = qdiv(qsub(qint(255), qint(dcofs)), qint(255));
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111 qsprint(dcscale, tmps, sizeof(tmps));
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112 printf("dcscale = %s\n", tmps);
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113
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114 if (ncode == 1) {
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115 // Number of samples for half of the pulse
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116 // Do division first so we don't overflow Q16.16
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117 shapesamples = qtoi(qmul(qdiv(qint(plen), qint(100)), qint(shapelen / 2)));
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118 // Number of samples for everything
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119 nsamples = shapesamples * 2 + slew1 + slew2;
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120 } else {
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121 shapesamples = plen / 2;
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122 nsamples = shapesamples * 2 * ncode + codegap * (ncode - 1) + slew1 + slew2;
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123 }
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124
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125 // Number of samples per step in the pulse shape
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126 stepsize = qdiv(qint(shapesamples), qint(shapelen));
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127 qsprint(stepsize, tmps, sizeof(tmps));
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128 printf("shapelen = %d shapesamples = %lu nsamples = %lu stepsize = %s\n", shapelen, shapesamples, nsamples, tmps);
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129
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130 if (nsamples > datalen) {
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131 printf("Pulse too long (%ld > %u)\n", nsamples, datalen);
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132 return 0;
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133 }
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134 if (shapesamples < 2) {
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135 printf("Pulse too short (%lu < %d)\n", shapesamples, 2);
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136 return 0;
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137 }
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138 if (qtoi(shapesamples) > 65535) {
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139 printf("Shape too long (%u > %d)\n", qtoi(shapesamples), 65535);
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140 return 0;
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141 }
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142 idx = 0;
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143
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144 // Up slew
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145 for (uint16_t i = 0; i < slew1; i++) {
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146 data[idx++] = qtoi(qdiv(qmul(qint(dcofs), qint(i)), qint(slew1)));
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147 ctrl[idx] |= PACTIVE;
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148 }
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149 for (uint16_t c = 0; c < ncode; c++) {
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150 if (c == 0)
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151 bit1startup = idx;
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152
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153 uint ctrltmp = PACTIVE;
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154 if (code[c] == '0')
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155 ctrltmp |= PHINV;
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156
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157 // Pulse up
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158 for (uint16_t i = 0; i < shapesamples; i++) {
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159 if (c == 0)
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160 data[idx++] = dcofs + qtoi(qmul(qint(shape[qtoi(qdiv(qint(i), stepsize))]), dcscale));
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161 else
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162 // Already done it before, just copy the previous instance
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163 data[idx++] = data[bit1startup + i];
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164 ctrl[idx] = ctrltmp;
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165 }
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166 if (c == 0)
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167 bit1stopup = idx - 1;
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168 // Pulse down
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169 // Since the pulse is symmetrical just copy the up slope in reverse
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170 for (uint16_t i = 0; i < shapesamples; i++) {
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171 data[idx++] = data[bit1stopup - i];
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172 // Could replace this with a separate loop to poke it into place
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173 // Similarly for TR switch when implemented
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174 if (i == 0 && c == 0)
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175 ctrl[idx] = ctrltmp | SENSE;
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176 else
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177 ctrl[idx] = ctrltmp;
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178 }
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179
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180 // Code gap
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181 if (c < ncode - 1)
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182 for (uint16_t i = 0; i < codegap; i++) {
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183 data[idx++] = dcofs;
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184 ctrl[idx] = ctrltmp;
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185 }
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186 }
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187
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188 // Down slew
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189 for (uint16_t i = 0; i < slew2; i++) {
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190 data[idx++] = qtoi(qdiv(qmul(qint(dcofs), qint(slew2 - i)), qint(slew2)));
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191 ctrl[idx] |= PACTIVE;
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192 }
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193 return idx - 1;
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194 }
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195
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196 // As per hello_interp.c
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197 void interp_test(uint8_t *data, const uint8_t *shape) {
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198 interp_config cfg;
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199 const int uv_fractional_bits = 12;
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200
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201 // Step size is 0.25 (ie stretching by 4x)
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202 unsigned step = (1 << uv_fractional_bits) / 4;
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203
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204 puts("interp_test\n");
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205 // Setup lane 0 to generate index into shape table
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206 // Mask start is 0 because we use 8 bit samples
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207 cfg = interp_default_config();
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208 interp_config_set_shift(&cfg, uv_fractional_bits);
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209 interp_config_set_mask(&cfg, 0, 32 - uv_fractional_bits);
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210 interp_config_set_blend(&cfg, true);
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211 interp_set_config(interp0, 0, &cfg);
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212
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213 // Setup lane 1 to LERP each sample pair
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214 cfg = interp_default_config();
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215 interp_config_set_shift(&cfg, uv_fractional_bits - 8);
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216 interp_config_set_signed(&cfg, false);
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217 interp_config_set_cross_input(&cfg, true); // unsigned blending
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218 interp_set_config(interp0, 1, &cfg);
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219
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220 interp0->accum[0] = 0; // Initial offset into shape table
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221 interp0->base[2] = (uintptr_t)shape; // Start of shape table
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222 for (unsigned i = 0; i < 122 * 4; i++) {
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223 // Get sample pair
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224 uint8_t *sample_pair = (uint8_t *) interp0->peek[2];
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225 // Ask lane 1 for a LERP, using the lane 0 accumulator
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226 interp0->base[0] = sample_pair[0];
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227 interp0->base[1] = sample_pair[1];
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228 uint32_t peek1 = interp0->peek[1];
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229 uint32_t add_raw1 = interp0->add_raw[1];
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230 data[i] = peek1;
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231 printf("%d\t(%lu%% between %d and %d) %lu\n",
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232 (int)peek1,
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233 100 * (add_raw1 & 0xff) / 0xff,
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234 sample_pair[0], sample_pair[1],
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235 interp_get_accumulator(interp0, 0));
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236 interp0->add_raw[0] = step;
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237 }
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238 puts("done");
3
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239 }
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240
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241 int
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242 main(void) {
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243 absolute_time_t then, now;
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244
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245 // Set sysclk to 120MHz
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246 set_sys_clock_khz(120000, true);
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247
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248 stdio_init_all();
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249 printf("\n\n\nIniting\n");
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250
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251 // Needed otherwise timer related functions hang under debugging
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252 // https://github.com/raspberrypi/pico-sdk/issues/1152#issuecomment-1418248639
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253 timer_hw->dbgpause = 0;
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254
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255 gpio_init(PICO_DEFAULT_LED_PIN);
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256 gpio_set_dir(PICO_DEFAULT_LED_PIN, GPIO_OUT);
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257
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258 //interp_test(pulse_data, shaped_trap);
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259
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260 uint32_t idx;
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261 uint16_t plen = 4000;
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262 char *code = "1110010";
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263 //char *code = "10";
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264 uint8_t codegap = 4;
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265 uint8_t slew1 = 10;
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266 uint8_t slew2 = 10;
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267 uint8_t dcofs = 110;
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268 memset(pulse_data, 0, sizeof(pulse_data));
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269 memset(pulse_ctrl, 0, sizeof(pulse_ctrl));
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270 then = get_absolute_time();
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271 if ((idx = compute_pulse(pulse_data, pulse_ctrl, sizeof(pulse_data),
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272 plen, code, strlen(code),
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273 shaped_trap, sizeof(shaped_trap),
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274 codegap, slew1, slew2, dcofs)) == 0) {
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275 printf("Failed to compute pulse\n");
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276 while (1)
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277 ;
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278 }
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279 now = get_absolute_time();
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280 printf("Pulse computation took %lld usec and created %lu samples\n", absolute_time_diff_us(then, now), idx);
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281
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282 pwm_config c = pwm_get_default_config();
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283 // 120MHz / 250 = 480kHz base
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284 // Maximum divisor is only 256 which limits the low end,
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285 // could further subdivide in the IRQ handler
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286 pwm_config_set_clkdiv_int(&c, 250);
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287 // 8Hz
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288 pwm_config_set_wrap(&c, 60000 - 1);
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289 pwm_init(slice_num, &c, true);
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290 pwm_clear_irq(slice_num);
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291 pwm_set_irq_enabled(slice_num, true);
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292 irq_set_exclusive_handler(PWM_IRQ_WRAP, pwm_wrap);
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293 irq_set_enabled(PWM_IRQ_WRAP, true);
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294 pwm_init(slice_num, &c, true);
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295
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296 // Load the clocked_input program, and configure a free state machine
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297 // to run the program.
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298 PIO pio = pio0;
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299 uint offset = pio_add_program(pio, &dac_program);
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300 uint sm = pio_claim_unused_sm(pio, true);
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301 // XXX: I would prefer starting at GPIO16 but in that case the top 2
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302 // bits don't seem to work
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303 // Clock divisor of 2 so it runs at 60MHz and
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304 // generates a 30MHz clock
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305 dac_program_init(pio, sm, offset, 14, 2);
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306
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307 // Configure a channel to write the same word (8 bits) repeatedly to PIO0
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308 // SM0's TX FIFO, paced by the data request signal from that peripheral.
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309 dma_chan = dma_claim_unused_channel(true);
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310 dma_channel_config dmac = dma_channel_get_default_config(dma_chan);
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311 // XXX: need to get pulse generator to pad to 32 bits
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312 channel_config_set_transfer_data_size(&dmac, DMA_SIZE_32);
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313 channel_config_set_read_increment(&dmac, true);
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314 channel_config_set_dreq(&dmac, DREQ_PIO0_TX0);
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315
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316 dma_channel_configure(
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317 dma_chan,
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318 &dmac,
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319 &pio0_hw->txf[0], // Write address (only need to set this once)
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320 NULL, // Don't provide a read address yet
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321 idx >> 2, // Transfer count
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322 false // Don't start yet
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323 );
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324
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325 // Tell the DMA to raise IRQ line 0 when the channel finishes a block
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326 dma_channel_set_irq0_enabled(dma_chan, true);
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327
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328 // Configure the processor to run dma_handler() when DMA IRQ 0 is asserted
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329 irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
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330 irq_set_enabled(DMA_IRQ_0, true);
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331
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332 // Everything else from this point is interrupt-driven. The processor has
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333 // time to sit and think about its early retirement -- maybe open a bakery?
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334 while (true) {
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335 dma_channel_wait_for_finish_blocking(dma_chan);
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336 gpio_put(PICO_DEFAULT_LED_PIN, 1);
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337 sleep_ms(100);
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338 gpio_put(PICO_DEFAULT_LED_PIN, 0);
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339 sleep_ms(100);
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340 }
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341
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342 __breakpoint();
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343 }