Binary file memec-test.ise has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/templates/coregen.xml	Fri Feb 24 14:01:26 2006 +0000
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
+	<Folder label="VERILOG Component Instantiation" treetype="folder">
+		<Template label="fifo" treetype="template">
+ 
+ 
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+ 
+fifo YourInstanceName (
+    .din(din),
+    .wr_en(wr_en),
+    .wr_clk(wr_clk),
+    .rd_en(rd_en),
+    .rd_clk(rd_clk),
+    .ainit(ainit),
+    .dout(dout),
+    .full(full),
+    .empty(empty));
+
+ 
+		</Template>
+	</Folder>
+	<Folder label="VHDL Component Instantiation" treetype="folder">
+		<Template label="fifo" treetype="template">
+ 
+ 
+-- The following code must appear in the VHDL architecture header:
+ 
+component fifo
+    port (
+    din: IN std_logic_VECTOR(3 downto 0);
+    wr_en: IN std_logic;
+    wr_clk: IN std_logic;
+    rd_en: IN std_logic;
+    rd_clk: IN std_logic;
+    ainit: IN std_logic;
+    dout: OUT std_logic_VECTOR(3 downto 0);
+    full: OUT std_logic;
+    empty: OUT std_logic);
+end component;
+
+
+
+ 
+-------------------------------------------------------------
+ 
+-- The following code must appear in the VHDL architecture body.
+-- Substitute your own instance name and net names.
+ 
+your_instance_name : fifo
+        port map (
+            din =&gt; din,
+            wr_en =&gt; wr_en,
+            wr_clk =&gt; wr_clk,
+            rd_en =&gt; rd_en,
+            rd_clk =&gt; rd_clk,
+            ainit =&gt; ainit,
+            dout =&gt; dout,
+            full =&gt; full,
+            empty =&gt; empty);
+ 
+		</Template>
+	</Folder>
+</RootFolder>

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/toplevel.v	Fri Feb 24 14:01:26 2006 +0000
@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:23:15 02/21/2006 
+// Design Name: 
+// Module Name:    toplevel 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module toplevel(CLK, PUSH, DIP, DISPLAY, LED, RIO_A03);
+   input CLK;
+   input [2:1] PUSH;
+   input [3:0] DIP;
+   output [6:0] DISPLAY;
+   output [3:0] LED;
+   output 	RIO_A03;
+ 	
+   wire 	 clk_div16;
+   wire [3:0] 	 FIFO_DIN;
+   wire [3:0] 	 FIFO_DOUT;
+   wire          FIFO_EMPTY;
+   wire          FIFO_FULL;
+   wire          FIFO_WREN;
+   wire          FIFO_WRCLK;
+   wire          FIFO_RDEN;
+   wire          FIFO_RDCLK;
+   wire          FIFO_RESET;
+
+   // Chipscope
+/*
+   wire [35:0] 	 control0;
+  */ 
+   // Input clock buffer
+   IBUFG     U1 ( .I(CLK), .O(clk_i));
+
+   // Clock Feedback
+   BUFG      U3 ( .I(clk0), .O(clk_fb));
+
+   // Output clock buffer
+   BUFG      U4 ( .I(clkdv), .O(clk_div16));
+
+   DCM #(
+	.CLKDV_DIVIDE(16.0),
+	.STARTUP_WAIT("TRUE")
+	) dcm_div16 (
+		     .CLK0(clk0),
+		     .CLKDV(clkdv),
+		     .CLKFB(clk_fb),
+		     .CLKIN(clk_i)
+		     );
+   
+   fifo_top FIFO (
+	      .din(FIFO_DIN),
+	      .wr_en(FIFO_WREN),
+	      .wr_clk(FIFO_WRCLK),
+	      .rd_en(FIFO_RDEN),
+	      .rd_clk(FIFO_RDCLK),
+	      .ainit(FIFO_RESET),
+	      .dout(FIFO_DOUT),
+	      .full(FIFO_FULL),
+	      .empty(FIFO_EMPTY)
+	      );
+
+   test TEST (
+	      .CLK(clk_div16),
+	      .PUSH(PUSH),
+	      .DIP(DIP),
+	      .DISPLAY(DISPLAY),
+	      .LED(LED),
+	      .FIFO_DIN(FIFO_DIN),
+	      .FIFO_DOUT(FIFO_DOUT),
+	      .FIFO_RDCLK(FIFO_RDCLK),
+	      .FIFO_RDEN(FIFO_RDEN),
+	      .FIFO_WRCLK(FIFO_WRCLK),
+	      .FIFO_WREN(FIFO_WREN),
+	      .FIFO_RESET(FIFO_RESET),
+	      .FIFO_FULL(FIFO_FULL),
+	      .FIFO_EMPTY(FIFO_EMPTY)
+	      );
+
+   // Chipscope control
+/*   icon ICON (
+	      .control0(control0)
+	      );
+*/   
+   // Chipscope ILA
+/*
+   ila ILA (
+	    .control(control0),
+	    .clk(clk_div16),
+	    .trig0({FIFO_DIN, FIFO_WREN, FIFO_WRCLK, FIFO_FULL, FIFO_EMPTY})
+	    );
+ */
+   assign 	 RIO_A03 = LED[0];
+ 	 
+endmodule // toplevel
+