Mercurial > ~darius > hgwebdir.cgi > memec-test
view fifo.edn @ 3:65ee845bf08c default tip
Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
Uses a FIFO and flashes some LEDs.
author | darius |
---|---|
date | Fri, 24 Feb 2006 14:01:26 +0000 |
parents | f88da01700da |
children |
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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2006 2 21 15 55 25) (author "Xilinx, Inc.") (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.1.02i; Cores Update # 1")))) (comment " This file is owned and controlled by Xilinx and must be used solely for design, simulation, implementation and creation of design files limited to Xilinx devices or technologies. Use with non-Xilinx devices or technologies is expressly prohibited and immediately terminates your license. XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS' SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Xilinx products are not intended for use in life support appliances, devices, or systems. Use in such applications are expressly prohibited. (c) Copyright 1995-2006 Xilinx, Inc. All rights reserved. ") (comment "Core parameters: ") (comment "c_use_blockmem = 1 ") (comment "c_rd_count_width = 2 ") (comment "c_has_wr_ack = 0 ") (comment "c_has_almost_full = 0 ") (comment "c_has_wr_err = 0 ") (comment "c_wr_err_low = 0 ") (comment "c_wr_ack_low = 0 ") (comment "c_data_width = 4 ") (comment "c_enable_rlocs = 0 ") (comment "c_rd_err_low = 0 ") (comment "c_rd_ack_low = 0 ") (comment "c_wr_count_width = 2 ") (comment "InstanceName = fifo ") (comment "c_has_rd_count = 0 ") (comment "c_has_almost_empty = 0 ") (comment "c_has_rd_ack = 0 ") (comment "c_has_wr_count = 0 ") (comment "c_fifo_depth = 15 ") (comment "c_has_rd_err = 0 ") (external xilinxun (edifLevel 0) (technology (numberDefinition)) (cell VCC (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port P (direction OUTPUT)) ) ) ) (cell GND (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port G (direction OUTPUT)) ) ) ) (cell FDC (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port D (direction INPUT)) (port C (direction INPUT)) (port CLR (direction INPUT)) (port Q (direction OUTPUT)) ) ) ) (cell FDCE (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port D (direction INPUT)) (port C (direction INPUT)) (port CE (direction INPUT)) (port CLR (direction INPUT)) (port Q (direction OUTPUT)) ) ) ) (cell FDP (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port D (direction INPUT)) (port C (direction INPUT)) (port PRE (direction INPUT)) (port Q (direction OUTPUT)) ) ) ) (cell FDPE (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port D (direction INPUT)) (port C (direction INPUT)) (port CE (direction INPUT)) (port PRE (direction INPUT)) (port Q (direction OUTPUT)) ) ) ) (cell LUT4 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port I0 (direction INPUT)) (port I1 (direction INPUT)) (port I2 (direction INPUT)) (port I3 (direction INPUT)) (port O (direction OUTPUT)) ) ) ) (cell MUXCY (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port DI (direction INPUT)) (port CI (direction INPUT)) (port S (direction INPUT)) (port O (direction OUTPUT)) ) ) ) (cell MUXCY_D (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port DI (direction INPUT)) (port CI (direction INPUT)) (port S (direction INPUT)) (port O (direction OUTPUT)) (port LO (direction OUTPUT)) ) ) ) (cell MUXCY_L (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port DI (direction INPUT)) (port CI (direction INPUT)) (port S (direction INPUT)) (port LO (direction OUTPUT)) ) ) ) (cell RAMB16_S4_S4 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port WEA (direction INPUT)) (port ENA (direction INPUT)) (port SSRA (direction INPUT)) (port CLKA (direction INPUT)) (port (rename DIA_0_ "DIA<0>") (direction INPUT)) (port (rename DIA_1_ "DIA<1>") (direction INPUT)) (port (rename DIA_2_ "DIA<2>") (direction INPUT)) (port (rename DIA_3_ "DIA<3>") (direction INPUT)) (port (rename DOA_0_ "DOA<0>") (direction OUTPUT)) (port (rename DOA_1_ "DOA<1>") (direction OUTPUT)) (port (rename DOA_2_ "DOA<2>") (direction OUTPUT)) (port (rename DOA_3_ "DOA<3>") (direction OUTPUT)) (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT)) (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT)) (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT)) (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT)) (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT)) (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT)) (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT)) (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT)) (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT)) (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT)) (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT)) (port (rename ADDRA_11_ "ADDRA<11>") (direction INPUT)) (port WEB (direction INPUT)) (port ENB (direction INPUT)) (port SSRB (direction INPUT)) (port CLKB (direction INPUT)) (port (rename DIB_0_ "DIB<0>") (direction INPUT)) (port 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) ) ) (cell XORCY (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port LI (direction INPUT)) (port CI (direction INPUT)) (port O (direction OUTPUT)) ) ) ) ) (library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) (cell fifo (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port ( array ( rename din "din<3:0>") 4 ) (direction INPUT)) (port ( rename wr_en "wr_en") (direction INPUT)) (port ( rename wr_clk "wr_clk") (direction INPUT)) (port ( rename rd_en "rd_en") (direction INPUT)) (port ( rename rd_clk "rd_clk") (direction INPUT)) (port ( rename ainit "ainit") (direction INPUT)) (port ( array ( rename dout "dout<3:0>") 4 ) (direction OUTPUT)) (port ( rename full "full") (direction OUTPUT)) (port ( rename empty "empty") (direction OUTPUT)) ) (contents (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) (instance B8 (viewRef view_1 (cellRef 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