`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:00:14 02/18/2006 
// Design Name: 
// Module Name:    test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(CLK, PUSH, DIP, DISPLAY, LED, FIFO_DIN, FIFO_DOUT, FIFO_RDCLK, FIFO_RDEN, FIFO_WRCLK, FIFO_WREN, FIFO_RESET, FIFO_FULL, FIFO_EMPTY);

   // Input Declarations
   input           CLK;          //surface-mount 50MHz oscillator
   input [2:1] 	   PUSH;         //push-button switches
   input [3:0] 	   DIP;          //DIP[3] is SW3[1] on the board
   input [3:0]     FIFO_DOUT;
   input           FIFO_FULL;
   input           FIFO_EMPTY;
  
   // Output Declarations
   output [6:0]    DISPLAY;      //7-segment display DD1
   output [3:0]    LED;          //user LEDs
   output [3:0]    FIFO_DIN;
   output          FIFO_RDCLK;
   output          FIFO_RDEN;
   output          FIFO_WRCLK;
   output          FIFO_WREN;
   output          FIFO_RESET;
   
   // Input Registers
   reg [3:0] 	   DIP_r [3:0]; // 4x4 array to hold registered versions of DIP
   reg [3:0] 	   DIP_d;       // debounced DIP
   reg [3:0] 	   PUSH1_r;     // registered version of PUSH1
   reg [3:0] 	   PUSH2_r;     // registered version of PUSH2
   reg             PUSH1_d;     // debounced PUSH1
   reg             PUSH2_d;     // debounced PUSH2

   // Output Registers
   reg [3:0] 	   LED;
   reg [6:0] 	   DISPLAY;
   reg 		   FIFO_WREN;
   reg 		   FIFO_WRCLK;
   reg 		   FIFO_RDEN;
   reg 		   FIFO_RDCLK;
   reg [3:0] 	   FIFO_DIN;
   reg 		   FIFO_RESET;
   
   // Other Registers
   reg [22:0] 	   sec_cnt; // Count clocks for sec_en
   reg             reset;   // high-asserted reset
   reg 		   ledtog;
   reg 		   direction;
 		   
   // Internal signals
   wire            sec_en; // Asserted on the second
   integer         i;
   
   // Register and debounce push buttons and switches
   // If the bouncy signal is high, 4 consecutive lows required to pull it low
   // If the bouncy signal is low, 4 consecutive highs required to pull it high
   always @(posedge CLK) begin
      PUSH1_r[0] <= PUSH[1];
      PUSH1_r[1] <= PUSH1_r[0];
      PUSH1_r[2] <= PUSH1_r[1];
      PUSH1_r[3] <= PUSH1_r[2];
      if(PUSH1_d)
        PUSH1_d <= |PUSH1_r;  
      else
        PUSH1_d <= &PUSH1_r;

      reset      <= ~PUSH1_d;

      PUSH2_r[0] <= PUSH[2];
      PUSH2_r[1] <= PUSH2_r[0];
      PUSH2_r[2] <= PUSH2_r[1];
      PUSH2_r[3] <= PUSH2_r[2];
      if(PUSH2_d)
        PUSH2_d <= |PUSH2_r;  
      else
        PUSH2_d <= &PUSH2_r;

      // Register the 4-bit DIP switch 4 times
      DIP_r[0]      <= DIP;
      DIP_r[1]      <= DIP_r[0];
      DIP_r[2]      <= DIP_r[1];
      DIP_r[3]      <= DIP_r[2];

      // Debounce the DIPs based on the register contents
      // For each bit, 0 through 3, switch polarity only when 4 opposite
      //     polarity is seen for four consecutive clocks.
      for (i = 0; i < 4; i = i+1)
	begin
           if(DIP_d[i])
             DIP_d[i] <= DIP_r[0][i] | DIP_r[1][i] | DIP_r[2][i] | DIP_r[3][i];
           else 
             DIP_d[i] <= DIP_r[0][i] & DIP_r[1][i] & DIP_r[2][i] & DIP_r[3][i];
	end

   end

   
   // Show FIFO status on LEDs
   always @(posedge CLK) begin
      if (reset) begin
	 LED <= 4'b0111;
	 DISPLAY <= 7'b1111111;
      end else begin
//	 LED <= (ledtog | (FIFO_EMPTY << 1) | (FIFO_FULL << 2) | (PUSH2_d << 3));
	 LED <= {PUSH2_d, ~FIFO_FULL, ~FIFO_EMPTY, ledtog};
	
	 if (PUSH2_d)
	    DISPLAY <= NUM2SEG(~DIP_d);
	 else
	    DISPLAY <= NUM2SEG(FIFO_DOUT);
      end // else: !if(reset)
   end // always @ (posedge CLK)
   
   always @(posedge CLK or negedge CLK) begin
      if (CLK) begin
	 FIFO_WRCLK <= 1;
	 FIFO_RDCLK <= 1;
      end else begin
	 FIFO_WRCLK <= 0;
	 FIFO_RDCLK <= 0;
      end
   end
   
   // Count 3.125Mhz clocks to drive the second tick
   always @(posedge CLK) begin
      if (reset) begin
	 ledtog <= 0;
         sec_cnt <= 0;
	 FIFO_DIN <= 0;
	 FIFO_WREN <= 0;
	 FIFO_RDEN <= 0;
	 FIFO_RESET <= 1;
	 direction <= 0; // Write
      end else begin
	 FIFO_RESET <= 0;
	 // Drive FIFO input from debounced DIP switches
	 FIFO_DIN <= ~(DIP_d);
	 
	 // Hit the second mark?
         if (sec_en) begin
            sec_cnt <= 0;
	    
	    // FIFO
	    if (FIFO_FULL)
	      direction <= 0;

	    if (FIFO_EMPTY)
	      direction <= 1;
	    
	    if (direction)
	      FIFO_WREN <= 1;
	    else
	      FIFO_RDEN <= 1;
	    
	    ledtog <= ~ledtog;
         end else begin // sec_en
            sec_cnt <= sec_cnt + 1;
	    FIFO_WREN <= 0;
	    FIFO_RDEN <= 0;
	 end
      end
   end // always @ (posedge CLK)
   
   // Create 1-second count
   assign   sec_en  = (sec_cnt == 22'd3_125_000);

   // Convert a number into hex for the 7 segment display
   function [6:0] NUM2SEG;
      input [3:0] num;
      begin
	 case (num)
	   0:    NUM2SEG   = ~(7'b0111111); 
	   1:    NUM2SEG   = ~(7'b0000110); 
	   2:    NUM2SEG   = ~(7'b1011011); 
	   3:    NUM2SEG   = ~(7'b1001111); 
	   4:    NUM2SEG   = ~(7'b1100110); 
	   5:    NUM2SEG   = ~(7'b1101101); 
	   6:    NUM2SEG   = ~(7'b1111101); 
	   7:    NUM2SEG   = ~(7'b0000111); 
	   8:    NUM2SEG   = ~(7'b1111111); 
	   9:    NUM2SEG   = ~(7'b1101111);
	   4'hA: NUM2SEG   = ~(7'b1110111); 
	   4'hb: NUM2SEG   = ~(7'b1111100); 
	   4'hC: NUM2SEG   = ~(7'b0111001); 
	   4'hd: NUM2SEG   = ~(7'b1011110); 
	   4'hE: NUM2SEG   = ~(7'b1111001); 
	   4'hF: NUM2SEG   = ~(7'b1110001); 
	   default:   NUM2SEG   = 7'b1111111;
	 endcase // case(~num)
      end
   endfunction
      
endmodule