# Specify a 50 MHz constraint with a Divide-by-16 in the DLL
NET      "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 50 MHz HIGH 50 %;

# I/O Placement and timing constraints

# Specify set-up and clk-out times
OFFSET = IN  5.0 ns BEFORE "CLK";
OFFSET = OUT 5.0 ns AFTER  "CLK";

# Locate DCM & BUFG to ensure they are on the same side as the clk pin
INST "dcm_div16" LOC = "DCM_X0Y1"  ;
INST "U3"            LOC = "BUFGMUX7"  ;
INST "U4"            LOC = "BUFGMUX6"  ;

# I/O input constraints
NET "CLK"   LOC = "P184" | IOSTANDARD = LVCMOS33; # SMT clock, JP30 must have jumper at 1-2
# NET "CLK"   LOC = "P183"; # clock socket

NET "PUSH<1>"      LOC = "P22";
NET "PUSH<2>"      LOC = "P24";
NET "PUSH<*>"      PULLUP | IOSTANDARD = LVCMOS33;

NET "DIP<3>"       LOC = "P26";
NET "DIP<2>"       LOC = "P27";
NET "DIP<1>"       LOC = "P28";
NET "DIP<0>"       LOC = "P29";
NET "DIP<*>"       PULLUP | IOSTANDARD = LVCMOS33;

# I/O Output Constraints
NET "DISPLAY<0>"   LOC = "P36"; # DISPLAY.1A
NET "DISPLAY<1>"   LOC = "P37"; # DISPLAY.1B
NET "DISPLAY<2>"   LOC = "P39"; # DISPLAY.1C
NET "DISPLAY<3>"   LOC = "P33"; # DISPLAY.1D
NET "DISPLAY<4>"   LOC = "P31"; # DISPLAY.1E
NET "DISPLAY<5>"   LOC = "P34"; # DISPLAY.1F
NET "DISPLAY<6>"   LOC = "P35"; # DISPLAY.1G
NET "DISPLAY<*>"   FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;

NET "LED<0>"       LOC = "P19";
NET "LED<1>"       LOC = "P18";
NET "LED<2>"       LOC = "P21";
NET "LED<3>"       LOC = "P20";
NET "LED<*>"       FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;

NET "RIO_A03"	   LOC = "P128" | IOSTANDARD = LVCMOS33 | FAST | DRIVE = 24;