--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/templates/coregen.xml	Fri Feb 24 14:01:26 2006 +0000
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
+	<Folder label="VERILOG Component Instantiation" treetype="folder">
+		<Template label="fifo" treetype="template">
+ 
+ 
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+ 
+fifo YourInstanceName (
+    .din(din),
+    .wr_en(wr_en),
+    .wr_clk(wr_clk),
+    .rd_en(rd_en),
+    .rd_clk(rd_clk),
+    .ainit(ainit),
+    .dout(dout),
+    .full(full),
+    .empty(empty));
+
+ 
+		</Template>
+	</Folder>
+	<Folder label="VHDL Component Instantiation" treetype="folder">
+		<Template label="fifo" treetype="template">
+ 
+ 
+-- The following code must appear in the VHDL architecture header:
+ 
+component fifo
+    port (
+    din: IN std_logic_VECTOR(3 downto 0);
+    wr_en: IN std_logic;
+    wr_clk: IN std_logic;
+    rd_en: IN std_logic;
+    rd_clk: IN std_logic;
+    ainit: IN std_logic;
+    dout: OUT std_logic_VECTOR(3 downto 0);
+    full: OUT std_logic;
+    empty: OUT std_logic);
+end component;
+
+
+
+ 
+-------------------------------------------------------------
+ 
+-- The following code must appear in the VHDL architecture body.
+-- Substitute your own instance name and net names.
+ 
+your_instance_name : fifo
+        port map (
+            din =&gt; din,
+            wr_en =&gt; wr_en,
+            wr_clk =&gt; wr_clk,
+            rd_en =&gt; rd_en,
+            rd_clk =&gt; rd_clk,
+            ainit =&gt; ainit,
+            dout =&gt; dout,
+            full =&gt; full,
+            empty =&gt; empty);
+ 
+		</Template>
+	</Folder>
+</RootFolder>