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comparison toplevel.ucf @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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0:7390b436dd20 1:f88da01700da
1 # Specify a 50 MHz constraint with a Divide-by-16 in the DLL
2 NET "CLK" TNM_NET = "CLK";
3 TIMESPEC "TS_CLK" = PERIOD "CLK" 50 MHz HIGH 50 %;
4
5 # I/O Placement and timing constraints
6
7 # Specify set-up and clk-out times
8 OFFSET = IN 5.0 ns BEFORE "CLK";
9 OFFSET = OUT 5.0 ns AFTER "CLK";
10
11 # Locate DCM & BUFG to ensure they are on the same side as the clk pin
12 INST "dcm_div16" LOC = "DCM_X0Y1" ;
13 INST "U3" LOC = "BUFGMUX7" ;
14 INST "U4" LOC = "BUFGMUX6" ;
15
16 # I/O input constraints
17 NET "CLK" LOC = "P184" | IOSTANDARD = LVCMOS33; # SMT clock, JP30 must have jumper at 1-2
18 # NET "CLK" LOC = "P183"; # clock socket
19
20 NET "PUSH<1>" LOC = "P22";
21 NET "PUSH<2>" LOC = "P24";
22 NET "PUSH<*>" PULLUP | IOSTANDARD = LVCMOS33;
23
24 NET "DIP<3>" LOC = "P26";
25 NET "DIP<2>" LOC = "P27";
26 NET "DIP<1>" LOC = "P28";
27 NET "DIP<0>" LOC = "P29";
28 NET "DIP<*>" PULLUP | IOSTANDARD = LVCMOS33;
29
30 # I/O Output Constraints
31 NET "DISPLAY<0>" LOC = "P36"; # DISPLAY.1A
32 NET "DISPLAY<1>" LOC = "P37"; # DISPLAY.1B
33 NET "DISPLAY<2>" LOC = "P39"; # DISPLAY.1C
34 NET "DISPLAY<3>" LOC = "P33"; # DISPLAY.1D
35 NET "DISPLAY<4>" LOC = "P31"; # DISPLAY.1E
36 NET "DISPLAY<5>" LOC = "P34"; # DISPLAY.1F
37 NET "DISPLAY<6>" LOC = "P35"; # DISPLAY.1G
38 NET "DISPLAY<*>" FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;
39
40 NET "LED<0>" LOC = "P19";
41 NET "LED<1>" LOC = "P18";
42 NET "LED<2>" LOC = "P21";
43 NET "LED<3>" LOC = "P20";
44 NET "LED<*>" FAST | DRIVE = 24 | IOSTANDARD = LVCMOS33;
45
46 NET "RIO_A03" LOC = "P128" | IOSTANDARD = LVCMOS33 | FAST | DRIVE = 24;