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comparison test_test.v @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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0:7390b436dd20 1:f88da01700da
1 `timescale 1ns / 1ps
2
3 ////////////////////////////////////////////////////////////////////////////////
4 // Company:
5 // Engineer:
6 //
7 // Create Date: 16:48:57 02/22/2006
8 // Design Name: test
9 // Module Name: test_test.v
10 // Project Name: Memec-test
11 // Target Device:
12 // Tool versions:
13 // Description:
14 //
15 // Verilog Test Fixture created by ISE for module: test
16 //
17 // Dependencies:
18 //
19 // Revision:
20 // Revision 0.01 - File Created
21 // Additional Comments:
22 //
23 ////////////////////////////////////////////////////////////////////////////////
24
25 module test_test_v;
26
27 // Inputs
28 reg CLK;
29 reg [2:1] PUSH;
30 reg [3:0] DIP;
31 reg [3:0] FIFO_DOUT;
32 reg FIFO_FULL;
33 reg FIFO_EMPTY;
34
35 // Outputs
36 wire [6:0] DISPLAY;
37 wire [3:0] LED;
38 wire [3:0] FIFO_DIN;
39 wire FIFO_RDCLK;
40 wire FIFO_RDEN;
41 wire FIFO_WRCLK;
42 wire FIFO_WREN;
43 wire FIFO_RESET;
44
45 // Instantiate the Unit Under Test (UUT)
46 test uut (
47 .CLK(CLK),
48 .PUSH(PUSH),
49 .DIP(DIP),
50 .DISPLAY(DISPLAY),
51 .LED(LED),
52 .FIFO_DIN(FIFO_DIN),
53 .FIFO_DOUT(FIFO_DOUT),
54 .FIFO_RDCLK(FIFO_RDCLK),
55 .FIFO_RDEN(FIFO_RDEN),
56 .FIFO_WRCLK(FIFO_WRCLK),
57 .FIFO_WREN(FIFO_WREN),
58 .FIFO_RESET(FIFO_RESET),
59 .FIFO_FULL(FIFO_FULL),
60 .FIFO_EMPTY(FIFO_EMPTY)
61 );
62
63 initial begin
64 // Initialize Inputs
65 CLK = 0;
66 PUSH = 0;
67 DIP = 0;
68 FIFO_DOUT = 0;
69 FIFO_FULL = 0;
70 FIFO_EMPTY = 0;
71
72 // Wait 100 ns for global reset to finish
73 #100;
74 end
75
76 always begin
77 #5 CLK = ~CLK; // Toggle clock every 5 ticks
78 end
79
80 endmodule
81