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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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0:7390b436dd20 1:f88da01700da
1 `timescale 1ns / 1ps
2 //////////////////////////////////////////////////////////////////////////////////
3 // Company:
4 // Engineer:
5 //
6 // Create Date: 14:00:14 02/18/2006
7 // Design Name:
8 // Module Name: test
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 module test(CLK, PUSH, DIP, DISPLAY, LED, FIFO_DIN, FIFO_DOUT, FIFO_RDCLK, FIFO_RDEN, FIFO_WRCLK, FIFO_WREN, FIFO_RESET, FIFO_FULL, FIFO_EMPTY);
22
23 // Input Declarations
24 input CLK; //surface-mount 50MHz oscillator
25 input [2:1] PUSH; //push-button switches
26 input [3:0] DIP; //DIP[3] is SW3[1] on the board
27 input [3:0] FIFO_DOUT;
28 input FIFO_FULL;
29 input FIFO_EMPTY;
30
31 // Output Declarations
32 output [6:0] DISPLAY; //7-segment display DD1
33 output [3:0] LED; //user LEDs
34 output [3:0] FIFO_DIN;
35 output FIFO_RDCLK;
36 output FIFO_RDEN;
37 output FIFO_WRCLK;
38 output FIFO_WREN;
39 output FIFO_RESET;
40
41 // Input Registers
42 reg [3:0] DIP_r [3:0]; // 4x4 array to hold registered versions of DIP
43 reg [3:0] DIP_d; // debounced DIP
44 reg [3:0] PUSH1_r; // registered version of PUSH1
45 reg [3:0] PUSH2_r; // registered version of PUSH2
46 reg PUSH1_d; // debounced PUSH1
47 reg PUSH2_d; // debounced PUSH2
48
49 // Output Registers
50 reg [3:0] LED;
51 reg [6:0] DISPLAY;
52 reg FIFO_WREN;
53 reg FIFO_WRCLK;
54 reg FIFO_RDEN;
55 reg FIFO_RDCLK;
56 reg [3:0] FIFO_DIN;
57 reg FIFO_RESET;
58
59 // Other Registers
60 reg [22:0] sec_cnt; // Count clocks for sec_en
61 reg reset; // high-asserted reset
62 reg ledtog;
63 reg direction;
64
65 // Internal signals
66 wire sec_en; // Asserted on the second
67 integer i;
68
69 // Register and debounce push buttons and switches
70 // If the bouncy signal is high, 4 consecutive lows required to pull it low
71 // If the bouncy signal is low, 4 consecutive highs required to pull it high
72 always @(posedge CLK) begin
73 PUSH1_r[0] <= PUSH[1];
74 PUSH1_r[1] <= PUSH1_r[0];
75 PUSH1_r[2] <= PUSH1_r[1];
76 PUSH1_r[3] <= PUSH1_r[2];
77 if(PUSH1_d)
78 PUSH1_d <= |PUSH1_r;
79 else
80 PUSH1_d <= &PUSH1_r;
81
82 reset <= ~PUSH1_d;
83
84 PUSH2_r[0] <= PUSH[2];
85 PUSH2_r[1] <= PUSH2_r[0];
86 PUSH2_r[2] <= PUSH2_r[1];
87 PUSH2_r[3] <= PUSH2_r[2];
88 if(PUSH2_d)
89 PUSH2_d <= |PUSH2_r;
90 else
91 PUSH2_d <= &PUSH2_r;
92
93 // Register the 4-bit DIP switch 4 times
94 DIP_r[0] <= DIP;
95 DIP_r[1] <= DIP_r[0];
96 DIP_r[2] <= DIP_r[1];
97 DIP_r[3] <= DIP_r[2];
98
99 // Debounce the DIPs based on the register contents
100 // For each bit, 0 through 3, switch polarity only when 4 opposite
101 // polarity is seen for four consecutive clocks.
102 for (i = 0; i < 4; i = i+1)
103 begin
104 if(DIP_d[i])
105 DIP_d[i] <= DIP_r[0][i] | DIP_r[1][i] | DIP_r[2][i] | DIP_r[3][i];
106 else
107 DIP_d[i] <= DIP_r[0][i] & DIP_r[1][i] & DIP_r[2][i] & DIP_r[3][i];
108 end
109
110 end
111
112
113 // Show FIFO status on LEDs
114 always @(posedge CLK) begin
115 if (reset) begin
116 LED <= 4'b0111;
117 DISPLAY <= 7'b1111111;
118 end else begin
119 // LED <= (ledtog | (FIFO_EMPTY << 1) | (FIFO_FULL << 2) | (PUSH2_d << 3));
120 LED <= {PUSH2_d, ~FIFO_FULL, ~FIFO_EMPTY, ledtog};
121
122 if (PUSH2_d)
123 DISPLAY <= NUM2SEG(~DIP_d);
124 else
125 DISPLAY <= NUM2SEG(FIFO_DOUT);
126 end // else: !if(reset)
127 end // always @ (posedge CLK)
128
129 always @(posedge CLK or negedge CLK) begin
130 if (CLK) begin
131 FIFO_WRCLK <= 1;
132 FIFO_RDCLK <= 1;
133 end else begin
134 FIFO_WRCLK <= 0;
135 FIFO_RDCLK <= 0;
136 end
137 end
138
139 // Count 3.125Mhz clocks to drive the second tick
140 always @(posedge CLK) begin
141 if (reset) begin
142 ledtog <= 0;
143 sec_cnt <= 0;
144 FIFO_DIN <= 0;
145 FIFO_WREN <= 0;
146 FIFO_RDEN <= 0;
147 FIFO_RESET <= 1;
148 direction <= 0; // Write
149 end else begin
150 FIFO_RESET <= 0;
151 // Drive FIFO input from debounced DIP switches
152 FIFO_DIN <= ~(DIP_d);
153
154 // Hit the second mark?
155 if (sec_en) begin
156 sec_cnt <= 0;
157
158 // FIFO
159 if (FIFO_FULL)
160 direction <= 0;
161
162 if (FIFO_EMPTY)
163 direction <= 1;
164
165 if (direction)
166 FIFO_WREN <= 1;
167 else
168 FIFO_RDEN <= 1;
169
170 ledtog <= ~ledtog;
171 end else begin // sec_en
172 sec_cnt <= sec_cnt + 1;
173 FIFO_WREN <= 0;
174 FIFO_RDEN <= 0;
175 end
176 end
177 end // always @ (posedge CLK)
178
179 // Create 1-second count
180 assign sec_en = (sec_cnt == 22'd3_125_000);
181
182 // Convert a number into hex for the 7 segment display
183 function [6:0] NUM2SEG;
184 input [3:0] num;
185 begin
186 case (num)
187 0: NUM2SEG = ~(7'b0111111);
188 1: NUM2SEG = ~(7'b0000110);
189 2: NUM2SEG = ~(7'b1011011);
190 3: NUM2SEG = ~(7'b1001111);
191 4: NUM2SEG = ~(7'b1100110);
192 5: NUM2SEG = ~(7'b1101101);
193 6: NUM2SEG = ~(7'b1111101);
194 7: NUM2SEG = ~(7'b0000111);
195 8: NUM2SEG = ~(7'b1111111);
196 9: NUM2SEG = ~(7'b1101111);
197 4'hA: NUM2SEG = ~(7'b1110111);
198 4'hb: NUM2SEG = ~(7'b1111100);
199 4'hC: NUM2SEG = ~(7'b0111001);
200 4'hd: NUM2SEG = ~(7'b1011110);
201 4'hE: NUM2SEG = ~(7'b1111001);
202 4'hF: NUM2SEG = ~(7'b1110001);
203 default: NUM2SEG = 7'b1111111;
204 endcase // case(~num)
205 end
206 endfunction
207
208 endmodule