Mercurial > ~darius > hgwebdir.cgi > memec-test
comparison fifo.vho @ 1:f88da01700da GSOFT-MEMEC-1-REL
Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
Uses a FIFO and flashes some LEDs.
| author | darius |
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| date | Fri, 24 Feb 2006 14:01:25 +0000 |
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| 0:7390b436dd20 | 1:f88da01700da |
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| 1 -------------------------------------------------------------------------------- | |
| 2 -- This file is owned and controlled by Xilinx and must be used -- | |
| 3 -- solely for design, simulation, implementation and creation of -- | |
| 4 -- design files limited to Xilinx devices or technologies. Use -- | |
| 5 -- with non-Xilinx devices or technologies is expressly prohibited -- | |
| 6 -- and immediately terminates your license. -- | |
| 7 -- -- | |
| 8 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- | |
| 9 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- | |
| 10 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- | |
| 11 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- | |
| 12 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- | |
| 13 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- | |
| 14 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- | |
| 15 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- | |
| 16 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- | |
| 17 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- | |
| 18 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- | |
| 19 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- | |
| 20 -- FOR A PARTICULAR PURPOSE. -- | |
| 21 -- -- | |
| 22 -- Xilinx products are not intended for use in life support -- | |
| 23 -- appliances, devices, or systems. Use in such applications are -- | |
| 24 -- expressly prohibited. -- | |
| 25 -- -- | |
| 26 -- (c) Copyright 1995-2006 Xilinx, Inc. -- | |
| 27 -- All rights reserved. -- | |
| 28 -------------------------------------------------------------------------------- | |
| 29 -- The following code must appear in the VHDL architecture header: | |
| 30 | |
| 31 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG | |
| 32 component fifo | |
| 33 port ( | |
| 34 din: IN std_logic_VECTOR(3 downto 0); | |
| 35 wr_en: IN std_logic; | |
| 36 wr_clk: IN std_logic; | |
| 37 rd_en: IN std_logic; | |
| 38 rd_clk: IN std_logic; | |
| 39 ainit: IN std_logic; | |
| 40 dout: OUT std_logic_VECTOR(3 downto 0); | |
| 41 full: OUT std_logic; | |
| 42 empty: OUT std_logic); | |
| 43 end component; | |
| 44 | |
| 45 -- FPGA Express Black Box declaration | |
| 46 attribute fpga_dont_touch: string; | |
| 47 attribute fpga_dont_touch of fifo: component is "true"; | |
| 48 | |
| 49 -- Synplicity black box declaration | |
| 50 attribute syn_black_box : boolean; | |
| 51 attribute syn_black_box of fifo: component is true; | |
| 52 | |
| 53 -- COMP_TAG_END ------ End COMPONENT Declaration ------------ | |
| 54 | |
| 55 -- The following code must appear in the VHDL architecture | |
| 56 -- body. Substitute your own instance name and net names. | |
| 57 | |
| 58 ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG | |
| 59 your_instance_name : fifo | |
| 60 port map ( | |
| 61 din => din, | |
| 62 wr_en => wr_en, | |
| 63 wr_clk => wr_clk, | |
| 64 rd_en => rd_en, | |
| 65 rd_clk => rd_clk, | |
| 66 ainit => ainit, | |
| 67 dout => dout, | |
| 68 full => full, | |
| 69 empty => empty); | |
| 70 -- INST_TAG_END ------ End INSTANTIATION Template ------------ | |
| 71 | |
| 72 -- You must compile the wrapper file fifo.vhd when simulating | |
| 73 -- the core, fifo. When compiling the wrapper file, be sure to | |
| 74 -- reference the XilinxCoreLib VHDL simulation library. For detailed | |
| 75 -- instructions, please refer to the "CORE Generator Help". | |
| 76 |