Mercurial > ~darius > hgwebdir.cgi > memec-test
comparison fifo.vhd @ 1:f88da01700da GSOFT-MEMEC-1-REL
Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
Uses a FIFO and flashes some LEDs.
| author | darius |
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| date | Fri, 24 Feb 2006 14:01:25 +0000 |
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| 0:7390b436dd20 | 1:f88da01700da |
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| 1 -------------------------------------------------------------------------------- | |
| 2 -- This file is owned and controlled by Xilinx and must be used -- | |
| 3 -- solely for design, simulation, implementation and creation of -- | |
| 4 -- design files limited to Xilinx devices or technologies. Use -- | |
| 5 -- with non-Xilinx devices or technologies is expressly prohibited -- | |
| 6 -- and immediately terminates your license. -- | |
| 7 -- -- | |
| 8 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- | |
| 9 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- | |
| 10 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- | |
| 11 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- | |
| 12 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- | |
| 13 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- | |
| 14 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- | |
| 15 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- | |
| 16 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- | |
| 17 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- | |
| 18 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- | |
| 19 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- | |
| 20 -- FOR A PARTICULAR PURPOSE. -- | |
| 21 -- -- | |
| 22 -- Xilinx products are not intended for use in life support -- | |
| 23 -- appliances, devices, or systems. Use in such applications are -- | |
| 24 -- expressly prohibited. -- | |
| 25 -- -- | |
| 26 -- (c) Copyright 1995-2006 Xilinx, Inc. -- | |
| 27 -- All rights reserved. -- | |
| 28 -------------------------------------------------------------------------------- | |
| 29 -- You must compile the wrapper file fifo.vhd when simulating | |
| 30 -- the core, fifo. When compiling the wrapper file, be sure to | |
| 31 -- reference the XilinxCoreLib VHDL simulation library. For detailed | |
| 32 -- instructions, please refer to the "CORE Generator Help". | |
| 33 | |
| 34 -- The synopsys directives "translate_off/translate_on" specified | |
| 35 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity | |
| 36 -- synthesis tools. Ensure they are correct for your synthesis tool(s). | |
| 37 | |
| 38 LIBRARY ieee; | |
| 39 USE ieee.std_logic_1164.ALL; | |
| 40 -- synopsys translate_off | |
| 41 Library XilinxCoreLib; | |
| 42 -- synopsys translate_on | |
| 43 ENTITY fifo IS | |
| 44 port ( | |
| 45 din: IN std_logic_VECTOR(3 downto 0); | |
| 46 wr_en: IN std_logic; | |
| 47 wr_clk: IN std_logic; | |
| 48 rd_en: IN std_logic; | |
| 49 rd_clk: IN std_logic; | |
| 50 ainit: IN std_logic; | |
| 51 dout: OUT std_logic_VECTOR(3 downto 0); | |
| 52 full: OUT std_logic; | |
| 53 empty: OUT std_logic); | |
| 54 END fifo; | |
| 55 | |
| 56 ARCHITECTURE fifo_a OF fifo IS | |
| 57 -- synopsys translate_off | |
| 58 component wrapped_fifo | |
| 59 port ( | |
| 60 din: IN std_logic_VECTOR(3 downto 0); | |
| 61 wr_en: IN std_logic; | |
| 62 wr_clk: IN std_logic; | |
| 63 rd_en: IN std_logic; | |
| 64 rd_clk: IN std_logic; | |
| 65 ainit: IN std_logic; | |
| 66 dout: OUT std_logic_VECTOR(3 downto 0); | |
| 67 full: OUT std_logic; | |
| 68 empty: OUT std_logic); | |
| 69 end component; | |
| 70 | |
| 71 -- Configuration specification | |
| 72 for all : wrapped_fifo use entity XilinxCoreLib.async_fifo_v6_1(behavioral) | |
| 73 generic map( | |
| 74 c_use_blockmem => 1, | |
| 75 c_rd_count_width => 2, | |
| 76 c_has_wr_ack => 0, | |
| 77 c_has_almost_full => 0, | |
| 78 c_has_wr_err => 0, | |
| 79 c_wr_err_low => 0, | |
| 80 c_wr_ack_low => 0, | |
| 81 c_data_width => 4, | |
| 82 c_enable_rlocs => 0, | |
| 83 c_rd_err_low => 0, | |
| 84 c_rd_ack_low => 0, | |
| 85 c_wr_count_width => 2, | |
| 86 c_has_rd_count => 0, | |
| 87 c_has_almost_empty => 0, | |
| 88 c_has_rd_ack => 0, | |
| 89 c_has_wr_count => 0, | |
| 90 c_fifo_depth => 15, | |
| 91 c_has_rd_err => 0); | |
| 92 -- synopsys translate_on | |
| 93 BEGIN | |
| 94 -- synopsys translate_off | |
| 95 U0 : wrapped_fifo | |
| 96 port map ( | |
| 97 din => din, | |
| 98 wr_en => wr_en, | |
| 99 wr_clk => wr_clk, | |
| 100 rd_en => rd_en, | |
| 101 rd_clk => rd_clk, | |
| 102 ainit => ainit, | |
| 103 dout => dout, | |
| 104 full => full, | |
| 105 empty => empty); | |
| 106 -- synopsys translate_on | |
| 107 | |
| 108 END fifo_a; | |
| 109 |