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comparison fifo.v @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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0:7390b436dd20 1:f88da01700da
1 /*******************************************************************************
2 * This file is owned and controlled by Xilinx and must be used *
3 * solely for design, simulation, implementation and creation of *
4 * design files limited to Xilinx devices or technologies. Use *
5 * with non-Xilinx devices or technologies is expressly prohibited *
6 * and immediately terminates your license. *
7 * *
8 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
9 * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
10 * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
11 * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
12 * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
13 * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
14 * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
15 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
16 * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
17 * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
18 * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
19 * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
20 * FOR A PARTICULAR PURPOSE. *
21 * *
22 * Xilinx products are not intended for use in life support *
23 * appliances, devices, or systems. Use in such applications are *
24 * expressly prohibited. *
25 * *
26 * (c) Copyright 1995-2006 Xilinx, Inc. *
27 * All rights reserved. *
28 *******************************************************************************/
29 // The synopsys directives "translate_off/translate_on" specified below are
30 // supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
31 // tools. Ensure they are correct for your synthesis tool(s).
32
33 // You must compile the wrapper file fifo.v when simulating
34 // the core, fifo. When compiling the wrapper file, be sure to
35 // reference the XilinxCoreLib Verilog simulation library. For detailed
36 // instructions, please refer to the "CORE Generator Help".
37
38 `timescale 1ns/1ps
39
40 module fifo(
41 din,
42 wr_en,
43 wr_clk,
44 rd_en,
45 rd_clk,
46 ainit,
47 dout,
48 full,
49 empty);
50
51
52 input [3 : 0] din;
53 input wr_en;
54 input wr_clk;
55 input rd_en;
56 input rd_clk;
57 input ainit;
58 output [3 : 0] dout;
59 output full;
60 output empty;
61
62 // synopsys translate_off
63
64 ASYNC_FIFO_V6_1 #(
65 4, // c_data_width
66 0, // c_enable_rlocs
67 15, // c_fifo_depth
68 0, // c_has_almost_empty
69 0, // c_has_almost_full
70 0, // c_has_rd_ack
71 0, // c_has_rd_count
72 0, // c_has_rd_err
73 0, // c_has_wr_ack
74 0, // c_has_wr_count
75 0, // c_has_wr_err
76 0, // c_rd_ack_low
77 2, // c_rd_count_width
78 0, // c_rd_err_low
79 1, // c_use_blockmem
80 0, // c_wr_ack_low
81 2, // c_wr_count_width
82 0) // c_wr_err_low
83 inst (
84 .DIN(din),
85 .WR_EN(wr_en),
86 .WR_CLK(wr_clk),
87 .RD_EN(rd_en),
88 .RD_CLK(rd_clk),
89 .AINIT(ainit),
90 .DOUT(dout),
91 .FULL(full),
92 .EMPTY(empty),
93 .ALMOST_FULL(),
94 .ALMOST_EMPTY(),
95 .WR_COUNT(),
96 .RD_COUNT(),
97 .RD_ACK(),
98 .RD_ERR(),
99 .WR_ACK(),
100 .WR_ERR());
101
102
103 // synopsys translate_on
104
105 // FPGA Express black box declaration
106 // synopsys attribute fpga_dont_touch "true"
107 // synthesis attribute fpga_dont_touch of fifo is "true"
108
109 // XST black box declaration
110 // box_type "black_box"
111 // synthesis attribute box_type of fifo is "black_box"
112
113 endmodule
114