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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
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2:14f09db71ed7 3:65ee845bf08c
1 `timescale 1ns / 1ps
2 //////////////////////////////////////////////////////////////////////////////////
3 // Company:
4 // Engineer:
5 //
6 // Create Date: 16:23:15 02/21/2006
7 // Design Name:
8 // Module Name: toplevel
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 module toplevel(CLK, PUSH, DIP, DISPLAY, LED, RIO_A03);
22 input CLK;
23 input [2:1] PUSH;
24 input [3:0] DIP;
25 output [6:0] DISPLAY;
26 output [3:0] LED;
27 output RIO_A03;
28
29 wire clk_div16;
30 wire [3:0] FIFO_DIN;
31 wire [3:0] FIFO_DOUT;
32 wire FIFO_EMPTY;
33 wire FIFO_FULL;
34 wire FIFO_WREN;
35 wire FIFO_WRCLK;
36 wire FIFO_RDEN;
37 wire FIFO_RDCLK;
38 wire FIFO_RESET;
39
40 // Chipscope
41 /*
42 wire [35:0] control0;
43 */
44 // Input clock buffer
45 IBUFG U1 ( .I(CLK), .O(clk_i));
46
47 // Clock Feedback
48 BUFG U3 ( .I(clk0), .O(clk_fb));
49
50 // Output clock buffer
51 BUFG U4 ( .I(clkdv), .O(clk_div16));
52
53 DCM #(
54 .CLKDV_DIVIDE(16.0),
55 .STARTUP_WAIT("TRUE")
56 ) dcm_div16 (
57 .CLK0(clk0),
58 .CLKDV(clkdv),
59 .CLKFB(clk_fb),
60 .CLKIN(clk_i)
61 );
62
63 fifo_top FIFO (
64 .din(FIFO_DIN),
65 .wr_en(FIFO_WREN),
66 .wr_clk(FIFO_WRCLK),
67 .rd_en(FIFO_RDEN),
68 .rd_clk(FIFO_RDCLK),
69 .ainit(FIFO_RESET),
70 .dout(FIFO_DOUT),
71 .full(FIFO_FULL),
72 .empty(FIFO_EMPTY)
73 );
74
75 test TEST (
76 .CLK(clk_div16),
77 .PUSH(PUSH),
78 .DIP(DIP),
79 .DISPLAY(DISPLAY),
80 .LED(LED),
81 .FIFO_DIN(FIFO_DIN),
82 .FIFO_DOUT(FIFO_DOUT),
83 .FIFO_RDCLK(FIFO_RDCLK),
84 .FIFO_RDEN(FIFO_RDEN),
85 .FIFO_WRCLK(FIFO_WRCLK),
86 .FIFO_WREN(FIFO_WREN),
87 .FIFO_RESET(FIFO_RESET),
88 .FIFO_FULL(FIFO_FULL),
89 .FIFO_EMPTY(FIFO_EMPTY)
90 );
91
92 // Chipscope control
93 /* icon ICON (
94 .control0(control0)
95 );
96 */
97 // Chipscope ILA
98 /*
99 ila ILA (
100 .control(control0),
101 .clk(clk_div16),
102 .trig0({FIFO_DIN, FIFO_WREN, FIFO_WRCLK, FIFO_FULL, FIFO_EMPTY})
103 );
104 */
105 assign RIO_A03 = LED[0];
106
107 endmodule // toplevel
108