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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
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2:14f09db71ed7 3:65ee845bf08c
1 <?xml version="1.0" encoding="UTF-8"?>
2 <RootFolder label="COREGEN" treetype="folder" language="COREGEN">
3 <Folder label="VERILOG Component Instantiation" treetype="folder">
4 <Template label="fifo" treetype="template">
5
6
7 // The following must be inserted into your Verilog file for this
8 // core to be instantiated. Change the instance name and port connections
9 // (in parentheses) to your own signal names.
10
11 fifo YourInstanceName (
12 .din(din),
13 .wr_en(wr_en),
14 .wr_clk(wr_clk),
15 .rd_en(rd_en),
16 .rd_clk(rd_clk),
17 .ainit(ainit),
18 .dout(dout),
19 .full(full),
20 .empty(empty));
21
22
23 </Template>
24 </Folder>
25 <Folder label="VHDL Component Instantiation" treetype="folder">
26 <Template label="fifo" treetype="template">
27
28
29 -- The following code must appear in the VHDL architecture header:
30
31 component fifo
32 port (
33 din: IN std_logic_VECTOR(3 downto 0);
34 wr_en: IN std_logic;
35 wr_clk: IN std_logic;
36 rd_en: IN std_logic;
37 rd_clk: IN std_logic;
38 ainit: IN std_logic;
39 dout: OUT std_logic_VECTOR(3 downto 0);
40 full: OUT std_logic;
41 empty: OUT std_logic);
42 end component;
43
44
45
46
47 -------------------------------------------------------------
48
49 -- The following code must appear in the VHDL architecture body.
50 -- Substitute your own instance name and net names.
51
52 your_instance_name : fifo
53 port map (
54 din =&gt; din,
55 wr_en =&gt; wr_en,
56 wr_clk =&gt; wr_clk,
57 rd_en =&gt; rd_en,
58 rd_clk =&gt; rd_clk,
59 ainit =&gt; ainit,
60 dout =&gt; dout,
61 full =&gt; full,
62 empty =&gt; empty);
63
64 </Template>
65 </Folder>
66 </RootFolder>