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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
parents f88da01700da
children
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 `timescale 1ns / 1ps
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2 //////////////////////////////////////////////////////////////////////////////////
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3 // Company:
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4 // Engineer:
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5 //
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6 // Create Date: 14:00:14 02/18/2006
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7 // Design Name:
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8 // Module Name: test
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9 // Project Name:
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10 // Target Devices:
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11 // Tool versions:
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12 // Description:
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13 //
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14 // Dependencies:
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15 //
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16 // Revision:
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17 // Revision 0.01 - File Created
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18 // Additional Comments:
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19 //
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20 //////////////////////////////////////////////////////////////////////////////////
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21 module test(CLK, PUSH, DIP, DISPLAY, LED, FIFO_DIN, FIFO_DOUT, FIFO_RDCLK, FIFO_RDEN, FIFO_WRCLK, FIFO_WREN, FIFO_RESET, FIFO_FULL, FIFO_EMPTY);
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22
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23 // Input Declarations
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24 input CLK; //surface-mount 50MHz oscillator
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25 input [2:1] PUSH; //push-button switches
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26 input [3:0] DIP; //DIP[3] is SW3[1] on the board
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27 input [3:0] FIFO_DOUT;
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28 input FIFO_FULL;
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29 input FIFO_EMPTY;
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30
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31 // Output Declarations
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32 output [6:0] DISPLAY; //7-segment display DD1
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33 output [3:0] LED; //user LEDs
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34 output [3:0] FIFO_DIN;
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35 output FIFO_RDCLK;
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36 output FIFO_RDEN;
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37 output FIFO_WRCLK;
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38 output FIFO_WREN;
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39 output FIFO_RESET;
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40
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41 // Input Registers
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42 reg [3:0] DIP_r [3:0]; // 4x4 array to hold registered versions of DIP
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43 reg [3:0] DIP_d; // debounced DIP
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44 reg [3:0] PUSH1_r; // registered version of PUSH1
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45 reg [3:0] PUSH2_r; // registered version of PUSH2
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46 reg PUSH1_d; // debounced PUSH1
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47 reg PUSH2_d; // debounced PUSH2
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48
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49 // Output Registers
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50 reg [3:0] LED;
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51 reg [6:0] DISPLAY;
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52 reg FIFO_WREN;
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53 reg FIFO_WRCLK;
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54 reg FIFO_RDEN;
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55 reg FIFO_RDCLK;
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56 reg [3:0] FIFO_DIN;
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57 reg FIFO_RESET;
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58
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59 // Other Registers
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60 reg [22:0] sec_cnt; // Count clocks for sec_en
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61 reg reset; // high-asserted reset
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62 reg ledtog;
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63 reg direction;
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64
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65 // Internal signals
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66 wire sec_en; // Asserted on the second
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67 integer i;
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68
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69 // Register and debounce push buttons and switches
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70 // If the bouncy signal is high, 4 consecutive lows required to pull it low
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71 // If the bouncy signal is low, 4 consecutive highs required to pull it high
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72 always @(posedge CLK) begin
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73 PUSH1_r[0] <= PUSH[1];
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74 PUSH1_r[1] <= PUSH1_r[0];
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75 PUSH1_r[2] <= PUSH1_r[1];
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76 PUSH1_r[3] <= PUSH1_r[2];
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77 if(PUSH1_d)
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78 PUSH1_d <= |PUSH1_r;
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79 else
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80 PUSH1_d <= &PUSH1_r;
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81
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82 reset <= ~PUSH1_d;
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83
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84 PUSH2_r[0] <= PUSH[2];
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85 PUSH2_r[1] <= PUSH2_r[0];
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86 PUSH2_r[2] <= PUSH2_r[1];
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87 PUSH2_r[3] <= PUSH2_r[2];
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88 if(PUSH2_d)
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89 PUSH2_d <= |PUSH2_r;
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90 else
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91 PUSH2_d <= &PUSH2_r;
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92
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93 // Register the 4-bit DIP switch 4 times
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94 DIP_r[0] <= DIP;
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95 DIP_r[1] <= DIP_r[0];
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96 DIP_r[2] <= DIP_r[1];
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97 DIP_r[3] <= DIP_r[2];
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98
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99 // Debounce the DIPs based on the register contents
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100 // For each bit, 0 through 3, switch polarity only when 4 opposite
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101 // polarity is seen for four consecutive clocks.
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102 for (i = 0; i < 4; i = i+1)
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103 begin
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104 if(DIP_d[i])
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105 DIP_d[i] <= DIP_r[0][i] | DIP_r[1][i] | DIP_r[2][i] | DIP_r[3][i];
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106 else
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107 DIP_d[i] <= DIP_r[0][i] & DIP_r[1][i] & DIP_r[2][i] & DIP_r[3][i];
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108 end
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109
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110 end
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111
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112
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113 // Show FIFO status on LEDs
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114 always @(posedge CLK) begin
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115 if (reset) begin
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116 LED <= 4'b0111;
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117 DISPLAY <= 7'b1111111;
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118 end else begin
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119 // LED <= (ledtog | (FIFO_EMPTY << 1) | (FIFO_FULL << 2) | (PUSH2_d << 3));
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120 LED <= {PUSH2_d, ~FIFO_FULL, ~FIFO_EMPTY, ledtog};
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121
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122 if (PUSH2_d)
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123 DISPLAY <= NUM2SEG(~DIP_d);
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124 else
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125 DISPLAY <= NUM2SEG(FIFO_DOUT);
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126 end // else: !if(reset)
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127 end // always @ (posedge CLK)
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128
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129 always @(posedge CLK or negedge CLK) begin
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130 if (CLK) begin
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131 FIFO_WRCLK <= 1;
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132 FIFO_RDCLK <= 1;
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133 end else begin
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134 FIFO_WRCLK <= 0;
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135 FIFO_RDCLK <= 0;
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136 end
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137 end
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138
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139 // Count 3.125Mhz clocks to drive the second tick
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140 always @(posedge CLK) begin
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141 if (reset) begin
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142 ledtog <= 0;
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143 sec_cnt <= 0;
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144 FIFO_DIN <= 0;
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145 FIFO_WREN <= 0;
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146 FIFO_RDEN <= 0;
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147 FIFO_RESET <= 1;
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148 direction <= 0; // Write
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149 end else begin
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150 FIFO_RESET <= 0;
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151 // Drive FIFO input from debounced DIP switches
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152 FIFO_DIN <= ~(DIP_d);
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153
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154 // Hit the second mark?
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155 if (sec_en) begin
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156 sec_cnt <= 0;
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157
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158 // FIFO
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159 if (FIFO_FULL)
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160 direction <= 0;
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161
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162 if (FIFO_EMPTY)
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163 direction <= 1;
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164
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165 if (direction)
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166 FIFO_WREN <= 1;
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167 else
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168 FIFO_RDEN <= 1;
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169
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170 ledtog <= ~ledtog;
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171 end else begin // sec_en
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172 sec_cnt <= sec_cnt + 1;
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173 FIFO_WREN <= 0;
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174 FIFO_RDEN <= 0;
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175 end
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176 end
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177 end // always @ (posedge CLK)
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178
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179 // Create 1-second count
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180 assign sec_en = (sec_cnt == 22'd3_125_000);
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181
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182 // Convert a number into hex for the 7 segment display
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183 function [6:0] NUM2SEG;
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184 input [3:0] num;
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185 begin
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186 case (num)
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187 0: NUM2SEG = ~(7'b0111111);
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188 1: NUM2SEG = ~(7'b0000110);
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189 2: NUM2SEG = ~(7'b1011011);
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190 3: NUM2SEG = ~(7'b1001111);
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191 4: NUM2SEG = ~(7'b1100110);
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192 5: NUM2SEG = ~(7'b1101101);
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193 6: NUM2SEG = ~(7'b1111101);
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194 7: NUM2SEG = ~(7'b0000111);
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195 8: NUM2SEG = ~(7'b1111111);
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196 9: NUM2SEG = ~(7'b1101111);
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197 4'hA: NUM2SEG = ~(7'b1110111);
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198 4'hb: NUM2SEG = ~(7'b1111100);
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199 4'hC: NUM2SEG = ~(7'b0111001);
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200 4'hd: NUM2SEG = ~(7'b1011110);
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201 4'hE: NUM2SEG = ~(7'b1111001);
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202 4'hF: NUM2SEG = ~(7'b1110001);
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203 default: NUM2SEG = 7'b1111111;
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204 endcase // case(~num)
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205 end
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206 endfunction
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207
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208 endmodule