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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
parents f88da01700da
children
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 `timescale 1ns / 1ps
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2 //////////////////////////////////////////////////////////////////////////////////
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3 // Company:
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4 // Engineer:
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5 //
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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6 // Create Date: 18:33:04 02/21/2006
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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7 // Design Name:
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8 // Module Name: fifo_top
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9 // Project Name:
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10 // Target Devices:
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11 // Tool versions:
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12 // Description:
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13 //
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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14 // Dependencies:
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15 //
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16 // Revision:
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17 // Revision 0.01 - File Created
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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18 // Additional Comments:
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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19 //
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20 //////////////////////////////////////////////////////////////////////////////////
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21 module fifo_top(din, wr_en, wr_clk, rd_en, rd_clk, ainit, dout, full, empty);
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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22 input [3:0] din;
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23 input wr_en;
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24 input wr_clk;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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25 input rd_en;
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26 input rd_clk;
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27 input ainit;
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28
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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29 output [3:0] dout;
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30 output full;
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31 output empty;
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32
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33 fifo FIFO (
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34 .din(din),
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35 .wr_en(wr_en),
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36 .wr_clk(wr_clk),
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37 .rd_en(rd_en),
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38 .rd_clk(rd_clk),
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39 .ainit(ainit),
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40 .dout(dout),
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41 .full(full),
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42 .empty(empty)
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43 );
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44
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45 endmodule