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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
parents f88da01700da
children
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 --------------------------------------------------------------------------------
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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2 -- This file is owned and controlled by Xilinx and must be used --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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3 -- solely for design, simulation, implementation and creation of --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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4 -- design files limited to Xilinx devices or technologies. Use --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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5 -- with non-Xilinx devices or technologies is expressly prohibited --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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6 -- and immediately terminates your license. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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7 -- --
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8 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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9 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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10 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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11 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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12 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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13 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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14 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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15 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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16 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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17 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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18 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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19 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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20 -- FOR A PARTICULAR PURPOSE. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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21 -- --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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22 -- Xilinx products are not intended for use in life support --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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23 -- appliances, devices, or systems. Use in such applications are --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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24 -- expressly prohibited. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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25 -- --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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26 -- (c) Copyright 1995-2006 Xilinx, Inc. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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27 -- All rights reserved. --
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28 --------------------------------------------------------------------------------
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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29 -- The following code must appear in the VHDL architecture header:
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30
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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31 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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32 component fifo
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33 port (
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34 din: IN std_logic_VECTOR(3 downto 0);
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35 wr_en: IN std_logic;
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36 wr_clk: IN std_logic;
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37 rd_en: IN std_logic;
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38 rd_clk: IN std_logic;
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39 ainit: IN std_logic;
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40 dout: OUT std_logic_VECTOR(3 downto 0);
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41 full: OUT std_logic;
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42 empty: OUT std_logic);
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43 end component;
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44
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45 -- FPGA Express Black Box declaration
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46 attribute fpga_dont_touch: string;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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47 attribute fpga_dont_touch of fifo: component is "true";
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48
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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49 -- Synplicity black box declaration
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50 attribute syn_black_box : boolean;
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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51 attribute syn_black_box of fifo: component is true;
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52
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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53 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
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54
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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55 -- The following code must appear in the VHDL architecture
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56 -- body. Substitute your own instance name and net names.
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57
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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58 ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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59 your_instance_name : fifo
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60 port map (
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61 din => din,
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62 wr_en => wr_en,
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63 wr_clk => wr_clk,
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64 rd_en => rd_en,
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65 rd_clk => rd_clk,
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66 ainit => ainit,
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67 dout => dout,
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68 full => full,
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69 empty => empty);
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70 -- INST_TAG_END ------ End INSTANTIATION Template ------------
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71
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72 -- You must compile the wrapper file fifo.vhd when simulating
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73 -- the core, fifo. When compiling the wrapper file, be sure to
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74 -- reference the XilinxCoreLib VHDL simulation library. For detailed
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75 -- instructions, please refer to the "CORE Generator Help".
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