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annotate fifo.vhd @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 --------------------------------------------------------------------------------
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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2 -- This file is owned and controlled by Xilinx and must be used --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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3 -- solely for design, simulation, implementation and creation of --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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4 -- design files limited to Xilinx devices or technologies. Use --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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5 -- with non-Xilinx devices or technologies is expressly prohibited --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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6 -- and immediately terminates your license. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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7 -- --
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8 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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9 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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10 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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11 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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12 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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13 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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14 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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15 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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16 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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17 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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18 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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19 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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20 -- FOR A PARTICULAR PURPOSE. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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21 -- --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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22 -- Xilinx products are not intended for use in life support --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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23 -- appliances, devices, or systems. Use in such applications are --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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24 -- expressly prohibited. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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25 -- --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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26 -- (c) Copyright 1995-2006 Xilinx, Inc. --
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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27 -- All rights reserved. --
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28 --------------------------------------------------------------------------------
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29 -- You must compile the wrapper file fifo.vhd when simulating
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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30 -- the core, fifo. When compiling the wrapper file, be sure to
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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32 -- instructions, please refer to the "CORE Generator Help".
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33
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34 -- The synopsys directives "translate_off/translate_on" specified
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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35 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
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37
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38 LIBRARY ieee;
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39 USE ieee.std_logic_1164.ALL;
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40 -- synopsys translate_off
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41 Library XilinxCoreLib;
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42 -- synopsys translate_on
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43 ENTITY fifo IS
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44 port (
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45 din: IN std_logic_VECTOR(3 downto 0);
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46 wr_en: IN std_logic;
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47 wr_clk: IN std_logic;
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48 rd_en: IN std_logic;
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49 rd_clk: IN std_logic;
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50 ainit: IN std_logic;
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51 dout: OUT std_logic_VECTOR(3 downto 0);
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52 full: OUT std_logic;
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53 empty: OUT std_logic);
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54 END fifo;
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55
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56 ARCHITECTURE fifo_a OF fifo IS
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57 -- synopsys translate_off
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58 component wrapped_fifo
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59 port (
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60 din: IN std_logic_VECTOR(3 downto 0);
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61 wr_en: IN std_logic;
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62 wr_clk: IN std_logic;
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63 rd_en: IN std_logic;
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64 rd_clk: IN std_logic;
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65 ainit: IN std_logic;
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66 dout: OUT std_logic_VECTOR(3 downto 0);
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67 full: OUT std_logic;
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68 empty: OUT std_logic);
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69 end component;
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70
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71 -- Configuration specification
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72 for all : wrapped_fifo use entity XilinxCoreLib.async_fifo_v6_1(behavioral)
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73 generic map(
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74 c_use_blockmem => 1,
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75 c_rd_count_width => 2,
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76 c_has_wr_ack => 0,
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77 c_has_almost_full => 0,
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78 c_has_wr_err => 0,
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79 c_wr_err_low => 0,
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80 c_wr_ack_low => 0,
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81 c_data_width => 4,
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82 c_enable_rlocs => 0,
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83 c_rd_err_low => 0,
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84 c_rd_ack_low => 0,
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85 c_wr_count_width => 2,
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86 c_has_rd_count => 0,
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87 c_has_almost_empty => 0,
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88 c_has_rd_ack => 0,
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89 c_has_wr_count => 0,
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90 c_fifo_depth => 15,
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91 c_has_rd_err => 0);
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92 -- synopsys translate_on
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93 BEGIN
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94 -- synopsys translate_off
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95 U0 : wrapped_fifo
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96 port map (
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97 din => din,
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98 wr_en => wr_en,
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99 wr_clk => wr_clk,
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100 rd_en => rd_en,
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101 rd_clk => rd_clk,
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102 ainit => ainit,
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103 dout => dout,
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104 full => full,
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105 empty => empty);
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106 -- synopsys translate_on
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107
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108 END fifo_a;
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109