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annotate fifo.v @ 1:f88da01700da GSOFT-MEMEC-1-REL

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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:25 +0000
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 /*******************************************************************************
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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2 * This file is owned and controlled by Xilinx and must be used *
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3 * solely for design, simulation, implementation and creation of *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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4 * design files limited to Xilinx devices or technologies. Use *
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5 * with non-Xilinx devices or technologies is expressly prohibited *
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6 * and immediately terminates your license. *
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7 * *
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8 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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9 * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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10 * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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11 * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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12 * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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13 * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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14 * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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15 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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16 * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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17 * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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18 * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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19 * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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20 * FOR A PARTICULAR PURPOSE. *
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21 * *
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22 * Xilinx products are not intended for use in life support *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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23 * appliances, devices, or systems. Use in such applications are *
f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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24 * expressly prohibited. *
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25 * *
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26 * (c) Copyright 1995-2006 Xilinx, Inc. *
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27 * All rights reserved. *
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28 *******************************************************************************/
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29 // The synopsys directives "translate_off/translate_on" specified below are
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30 // supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
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31 // tools. Ensure they are correct for your synthesis tool(s).
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32
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33 // You must compile the wrapper file fifo.v when simulating
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34 // the core, fifo. When compiling the wrapper file, be sure to
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35 // reference the XilinxCoreLib Verilog simulation library. For detailed
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36 // instructions, please refer to the "CORE Generator Help".
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37
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38 `timescale 1ns/1ps
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39
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40 module fifo(
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41 din,
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42 wr_en,
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43 wr_clk,
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44 rd_en,
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45 rd_clk,
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46 ainit,
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47 dout,
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48 full,
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49 empty);
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50
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51
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52 input [3 : 0] din;
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53 input wr_en;
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54 input wr_clk;
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55 input rd_en;
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56 input rd_clk;
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57 input ainit;
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58 output [3 : 0] dout;
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59 output full;
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60 output empty;
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61
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62 // synopsys translate_off
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63
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64 ASYNC_FIFO_V6_1 #(
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65 4, // c_data_width
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66 0, // c_enable_rlocs
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67 15, // c_fifo_depth
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68 0, // c_has_almost_empty
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69 0, // c_has_almost_full
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70 0, // c_has_rd_ack
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71 0, // c_has_rd_count
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72 0, // c_has_rd_err
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73 0, // c_has_wr_ack
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74 0, // c_has_wr_count
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75 0, // c_has_wr_err
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76 0, // c_rd_ack_low
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77 2, // c_rd_count_width
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78 0, // c_rd_err_low
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79 1, // c_use_blockmem
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80 0, // c_wr_ack_low
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81 2, // c_wr_count_width
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82 0) // c_wr_err_low
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83 inst (
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84 .DIN(din),
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85 .WR_EN(wr_en),
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86 .WR_CLK(wr_clk),
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87 .RD_EN(rd_en),
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88 .RD_CLK(rd_clk),
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89 .AINIT(ainit),
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90 .DOUT(dout),
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91 .FULL(full),
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92 .EMPTY(empty),
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93 .ALMOST_FULL(),
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94 .ALMOST_EMPTY(),
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95 .WR_COUNT(),
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96 .RD_COUNT(),
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97 .RD_ACK(),
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98 .RD_ERR(),
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99 .WR_ACK(),
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100 .WR_ERR());
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101
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102
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103 // synopsys translate_on
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104
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105 // FPGA Express black box declaration
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106 // synopsys attribute fpga_dont_touch "true"
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107 // synthesis attribute fpga_dont_touch of fifo is "true"
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108
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109 // XST black box declaration
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110 // box_type "black_box"
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111 // synthesis attribute box_type of fifo is "black_box"
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112
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113 endmodule
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114