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Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
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65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 `timescale 1ns / 1ps
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2 //////////////////////////////////////////////////////////////////////////////////
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3 // Company:
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4 // Engineer:
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5 //
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6 // Create Date: 16:23:15 02/21/2006
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7 // Design Name:
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8 // Module Name: toplevel
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9 // Project Name:
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10 // Target Devices:
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11 // Tool versions:
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12 // Description:
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13 //
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14 // Dependencies:
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15 //
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16 // Revision:
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17 // Revision 0.01 - File Created
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18 // Additional Comments:
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19 //
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20 //////////////////////////////////////////////////////////////////////////////////
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21 module toplevel(CLK, PUSH, DIP, DISPLAY, LED, RIO_A03);
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22 input CLK;
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23 input [2:1] PUSH;
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24 input [3:0] DIP;
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25 output [6:0] DISPLAY;
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26 output [3:0] LED;
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27 output RIO_A03;
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28
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29 wire clk_div16;
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30 wire [3:0] FIFO_DIN;
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31 wire [3:0] FIFO_DOUT;
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32 wire FIFO_EMPTY;
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33 wire FIFO_FULL;
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34 wire FIFO_WREN;
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35 wire FIFO_WRCLK;
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36 wire FIFO_RDEN;
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37 wire FIFO_RDCLK;
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38 wire FIFO_RESET;
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39
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40 // Chipscope
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41 /*
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42 wire [35:0] control0;
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43 */
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44 // Input clock buffer
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45 IBUFG U1 ( .I(CLK), .O(clk_i));
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46
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47 // Clock Feedback
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48 BUFG U3 ( .I(clk0), .O(clk_fb));
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49
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50 // Output clock buffer
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51 BUFG U4 ( .I(clkdv), .O(clk_div16));
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52
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53 DCM #(
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54 .CLKDV_DIVIDE(16.0),
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55 .STARTUP_WAIT("TRUE")
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56 ) dcm_div16 (
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57 .CLK0(clk0),
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58 .CLKDV(clkdv),
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59 .CLKFB(clk_fb),
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60 .CLKIN(clk_i)
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61 );
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62
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63 fifo_top FIFO (
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64 .din(FIFO_DIN),
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65 .wr_en(FIFO_WREN),
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66 .wr_clk(FIFO_WRCLK),
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67 .rd_en(FIFO_RDEN),
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68 .rd_clk(FIFO_RDCLK),
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69 .ainit(FIFO_RESET),
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70 .dout(FIFO_DOUT),
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71 .full(FIFO_FULL),
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72 .empty(FIFO_EMPTY)
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73 );
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74
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75 test TEST (
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76 .CLK(clk_div16),
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77 .PUSH(PUSH),
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78 .DIP(DIP),
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79 .DISPLAY(DISPLAY),
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80 .LED(LED),
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81 .FIFO_DIN(FIFO_DIN),
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82 .FIFO_DOUT(FIFO_DOUT),
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83 .FIFO_RDCLK(FIFO_RDCLK),
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84 .FIFO_RDEN(FIFO_RDEN),
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85 .FIFO_WRCLK(FIFO_WRCLK),
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86 .FIFO_WREN(FIFO_WREN),
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87 .FIFO_RESET(FIFO_RESET),
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88 .FIFO_FULL(FIFO_FULL),
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89 .FIFO_EMPTY(FIFO_EMPTY)
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90 );
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91
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92 // Chipscope control
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93 /* icon ICON (
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94 .control0(control0)
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95 );
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96 */
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97 // Chipscope ILA
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98 /*
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99 ila ILA (
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100 .control(control0),
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101 .clk(clk_div16),
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102 .trig0({FIFO_DIN, FIFO_WREN, FIFO_WRCLK, FIFO_FULL, FIFO_EMPTY})
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103 );
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104 */
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105 assign RIO_A03 = LED[0];
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106
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107 endmodule // toplevel
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108