Mercurial > ~darius > hgwebdir.cgi > memec-test

annotate templates/coregen.xml @ 3:65ee845bf08c default tip

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Initial import of test project for Memec 3SxLC board with Xilinx XC3S400. Uses a FIFO and flashes some LEDs.
author darius
date Fri, 24 Feb 2006 14:01:26 +0000
parents
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
3
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
1 <?xml version="1.0" encoding="UTF-8"?>
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
2 <RootFolder label="COREGEN" treetype="folder" language="COREGEN">
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
3 <Folder label="VERILOG Component Instantiation" treetype="folder">
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
4 <Template label="fifo" treetype="template">
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
5
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
6
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
7 // The following must be inserted into your Verilog file for this
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
8 // core to be instantiated. Change the instance name and port connections
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
9 // (in parentheses) to your own signal names.
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
10
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
11 fifo YourInstanceName (
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
12 .din(din),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
13 .wr_en(wr_en),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
14 .wr_clk(wr_clk),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
15 .rd_en(rd_en),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
16 .rd_clk(rd_clk),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
17 .ainit(ainit),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
18 .dout(dout),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
19 .full(full),
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
20 .empty(empty));
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
21
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
22
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
23 </Template>
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
24 </Folder>
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
25 <Folder label="VHDL Component Instantiation" treetype="folder">
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
26 <Template label="fifo" treetype="template">
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
27
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
28
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
29 -- The following code must appear in the VHDL architecture header:
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
30
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
31 component fifo
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
32 port (
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
33 din: IN std_logic_VECTOR(3 downto 0);
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
34 wr_en: IN std_logic;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
35 wr_clk: IN std_logic;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
36 rd_en: IN std_logic;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
37 rd_clk: IN std_logic;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
38 ainit: IN std_logic;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
39 dout: OUT std_logic_VECTOR(3 downto 0);
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
40 full: OUT std_logic;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
41 empty: OUT std_logic);
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
42 end component;
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
43
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
44
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
45
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
46
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
47 -------------------------------------------------------------
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
48
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
49 -- The following code must appear in the VHDL architecture body.
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
50 -- Substitute your own instance name and net names.
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
51
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
52 your_instance_name : fifo
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
53 port map (
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
54 din =&gt; din,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
55 wr_en =&gt; wr_en,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
56 wr_clk =&gt; wr_clk,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
57 rd_en =&gt; rd_en,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
58 rd_clk =&gt; rd_clk,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
59 ainit =&gt; ainit,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
60 dout =&gt; dout,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
61 full =&gt; full,
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
62 empty =&gt; empty);
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
63
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
64 </Template>
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
65 </Folder>
65ee845bf08c Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
darius
parents:
diff changeset
66 </RootFolder>