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annotate test_test.v @ 2:14f09db71ed7

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Added tag GSOFT-MEMEC-1-REL for changeset f88da01700da
author darius@midget.dons.net.au
date Tue, 23 Oct 2007 10:08:35 +0930
parents f88da01700da
children
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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1 `timescale 1ns / 1ps
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3 ////////////////////////////////////////////////////////////////////////////////
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4 // Company:
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5 // Engineer:
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6 //
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7 // Create Date: 16:48:57 02/22/2006
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8 // Design Name: test
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9 // Module Name: test_test.v
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10 // Project Name: Memec-test
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11 // Target Device:
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12 // Tool versions:
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13 // Description:
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14 //
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15 // Verilog Test Fixture created by ISE for module: test
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16 //
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17 // Dependencies:
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18 //
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19 // Revision:
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20 // Revision 0.01 - File Created
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21 // Additional Comments:
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22 //
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23 ////////////////////////////////////////////////////////////////////////////////
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f88da01700da Initial import of test project for Memec 3SxLC board with Xilinx XC3S400.
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25 module test_test_v;
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26
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27 // Inputs
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28 reg CLK;
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29 reg [2:1] PUSH;
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30 reg [3:0] DIP;
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31 reg [3:0] FIFO_DOUT;
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32 reg FIFO_FULL;
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33 reg FIFO_EMPTY;
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34
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35 // Outputs
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36 wire [6:0] DISPLAY;
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37 wire [3:0] LED;
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38 wire [3:0] FIFO_DIN;
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39 wire FIFO_RDCLK;
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40 wire FIFO_RDEN;
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41 wire FIFO_WRCLK;
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42 wire FIFO_WREN;
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43 wire FIFO_RESET;
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44
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45 // Instantiate the Unit Under Test (UUT)
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46 test uut (
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47 .CLK(CLK),
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48 .PUSH(PUSH),
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49 .DIP(DIP),
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50 .DISPLAY(DISPLAY),
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51 .LED(LED),
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52 .FIFO_DIN(FIFO_DIN),
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53 .FIFO_DOUT(FIFO_DOUT),
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54 .FIFO_RDCLK(FIFO_RDCLK),
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55 .FIFO_RDEN(FIFO_RDEN),
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56 .FIFO_WRCLK(FIFO_WRCLK),
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57 .FIFO_WREN(FIFO_WREN),
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58 .FIFO_RESET(FIFO_RESET),
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59 .FIFO_FULL(FIFO_FULL),
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60 .FIFO_EMPTY(FIFO_EMPTY)
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61 );
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62
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63 initial begin
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64 // Initialize Inputs
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65 CLK = 0;
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66 PUSH = 0;
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67 DIP = 0;
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68 FIFO_DOUT = 0;
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69 FIFO_FULL = 0;
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70 FIFO_EMPTY = 0;
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71
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72 // Wait 100 ns for global reset to finish
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73 #100;
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74 end
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76 always begin
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77 #5 CLK = ~CLK; // Toggle clock every 5 ticks
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78 end
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80 endmodule
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