# HG changeset patch
# User darius
# Date 1089620442 -34200
# Node ID f9a085a0ba9320acd7f12461b7433bf4588cd85b
# Parent  a940431af6f50b81f73c159cf8b7e9e18631201b
Change the 1 wire routines to mostly C with assembly delay routines
for ease of portability.


diff -r a940431af6f5 -r f9a085a0ba93 1wire-delay.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/1wire-delay.h	Mon Jul 12 17:50:42 2004 +0930
@@ -0,0 +1,143 @@
+/*
+ * Delay routines for the 1 wire bus
+ * Search routine is copied from the Dallas owpd library with mods.
+ *
+ * $Id$
+ *
+ * Copyright (c) 2004
+ *      Daniel O'Connor <darius@dons.net.au>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Note that all these routines are clock speed sensitive!
+ * (4Mhz AT908515)
+ */
+
+#if (XTAL_CPU == 4000000)
+/* 6 usec */
+#define DELAY_A	asm volatile(	\
+	"ldi r21, 6\n\t"	\
+	"L_%=: nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 64 usec */
+#define DELAY_B asm volatile(	\
+	"ldi r21, 32\n\t"	\
+	"L_%=: nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 60 usec */
+#define DELAY_C asm volatile(	\
+	"ldi r21, 30\n\t"	\
+	"L_%=: nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 10 usec */
+#define DELAY_D asm volatile(	\
+	"ldi r21, 9\n\t"	\
+	"L_%=: nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 9 usec */
+#define DELAY_E asm volatile(	\
+	"ldi r21, 8\n\t"	\
+	"L_%=: nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 55 usec */
+#define DELAY_F asm volatile(	\
+	"ldi r21, 27\n\t"	\
+	"L_%=: nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 0 usec */    
+#define DELAY_G
+
+/* 480 usec */
+#define DELAY_H asm volatile(	\
+	"ldi r21, 120\n\t"	\
+	"L_%=: nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+
+/* 70 usec */    
+#define DELAY_I asm volatile(	\
+	"ldi r21, 35\n\t"	\
+	"L_%=: nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"nop\n\t"		\
+	"dec r21\n\t"		\
+	"brne L_%=\n\t"		\
+	::: "r21");
+#else
+#error No 1 wire delay routines for selected clock speed
+#endif
+
diff -r a940431af6f5 -r f9a085a0ba93 1wire.c
--- a/1wire.c	Mon Jul 12 16:49:21 2004 +0930
+++ b/1wire.c	Mon Jul 12 17:50:42 2004 +0930
@@ -2,6 +2,8 @@
  * Various 1 wire routines
  * Search routine is copied from the Dallas owpd library with mods.
  *
+ * $Id$
+ *
  * Copyright (c) 2004
  *      Daniel O'Connor <darius@dons.net.au>.  All rights reserved.
  *
@@ -32,6 +34,7 @@
 #include <avr/pgmspace.h>
 
 #include "1wire.h"
+#include "1wire-delay.h"
 
 void		uart_putsP(const char *addr);
 void		uart_puts(const char *addr);
@@ -137,61 +140,17 @@
 OWWriteBit(int bit) {
     OWdelay();
     if (bit) {
-	asm volatile (
-	    /* Drive bus low */
-	    "cbi %[out], %[pin]\n\t"
-	    "sbi %[ddr], %[pin]\n\t"
-	    /* Delay A (6 usec) */
-	    "ldi r21, 1\n\t"
-	    "loopA:\n\t"
-	    "nop\n\t"
-	    "dec r21\n\t"
-	    "brne loopA\n\t"
-	    /* Release bus */
-	    "cbi %[ddr], %[pin]\n\t"
-	    /* Delay B (64 usec) */
-	    "ldi r21, 32\n\t"
-	    "loopB:\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "dec r21\n\t"
-	    "brne loopB\n\t"
-	    :						/* Outputs */
-	    : [out] "I" (_SFR_IO_ADDR(OWIREOUTPORT)),	/* Inputs */
-	      [ddr] "I" (_SFR_IO_ADDR(OWIREDDR)),
-	      [pin] "I" (OWIREOUTPIN)
-	    : "r21");					/* Clobbers */
+	OWIREOUTPORT &= ~(_BV(OWIREOUTPIN));
+	OWIREDDR |= _BV(OWIREOUTPIN);
+	DELAY_A;
+	OWIREDDR &= ~(_BV(OWIREOUTPIN));
+	DELAY_B;
     } else {
-	asm volatile (
-	    /* Drive bus low */
-	    "cbi %[out], %[pin]\n\t"
-	    "sbi %[ddr], %[pin]\n\t"
-	    /* Delay C (60 usec) */
-	    "ldi r21, 30\n\t"
-	    "loopC:\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "nop\n\t"
-	    "dec r21\n\t"
-	    "brne loopC\n\t"
-	    /* Release bus */
-	    "cbi %[ddr], %[pin]\n\t"
-	    /* Delay D (10 usec) */
-	    "ldi r21, 9\n\t"
-	    "loopD:\n\t"
-	    "nop\n\t"
-	    "dec r21\n\t"
-	    "brne loopD\n\t"
-	    :						/* Outputs */
-	    : [out] "I" (_SFR_IO_ADDR(OWIREOUTPORT)),	/* Inputs */
-	      [ddr] "I" (_SFR_IO_ADDR(OWIREDDR)),
-	      [pin] "I" (OWIREOUTPIN)
-	    : "r21");					/* Clobbers */
+	OWIREOUTPORT &= ~(_BV(OWIREOUTPIN));
+	OWIREDDR |= _BV(OWIREOUTPIN);
+	DELAY_C;
+	OWIREDDR &= ~(_BV(OWIREOUTPIN));
+	DELAY_D;
     }
 }
 
@@ -200,60 +159,14 @@
  */
 int
 OWReadBit(void) {
-    uint8_t	result;
-
     OWdelay();
-    
-    asm volatile (
-	/* Drive bus low */
-	"cbi %[out], %[opin]\n\t"
-	"sbi %[ddr], %[opin]\n\t"
-	/* Delay A (6 usec) */
-	"ldi r21, 1\n\t"
-	"loopA1:\n\t"
-	"dec r21\n\t"
-	"brne loopA1\n\t"
-	/* Release bus */
-	"cbi %[ddr], %[opin]\n\t"
-	/* Delay E (9 usec) */
-	"ldi r21, 8\n\t"
-	"loopE:\n\t"
-	"nop\n\t"
-	"dec r21\n\t"
-	"brne loopE\n\t"
-	/* Sample */
-	"ldi %[res], 0\n\t"
-	"sbic %[in], %[ipin]\n\t"
-	"ldi %[res], 1\n\t"
 
-	/* Delay F (55 usec) */
-	"ldi r21, 27\n\t"
-	"loopF:\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"dec r21\n\t"
-	"brne loopF\n\t"
-
-	: [res]  "=r" (result) 				/* Outputs */
-	: [out]  "I" (_SFR_IO_ADDR(OWIREOUTPORT)),	/* Inputs */
-	  [ddr]  "I" (_SFR_IO_ADDR(OWIREDDR)),
-	  [opin] "I" (OWIREOUTPIN),
-	  [in]   "I" (_SFR_IO_ADDR(OWIREINPORT)),
-	  [ipin] "I" (OWIREINPIN)	
-	: "r21");					/* Clobbers */
-
-    return(result);
+    OWIREOUTPORT &= ~(_BV(OWIREOUTPIN));
+    OWIREDDR |= _BV(OWIREOUTPIN);
+    DELAY_A;
+    OWIREDDR &= ~(_BV(OWIREOUTPIN));
+    DELAY_E;
+    return(OWIREINPORT & _BV(OWIREINPIN) ? 1 : 0);
 }
 
 /*-----------------------------------------------------------------------------
diff -r a940431af6f5 -r f9a085a0ba93 1wire.h
--- a/1wire.h	Mon Jul 12 16:49:21 2004 +0930
+++ b/1wire.h	Mon Jul 12 17:50:42 2004 +0930
@@ -1,4 +1,9 @@
-/* Copyright (c) 2004
+/*
+ * 1 wire header code
+ *
+ * $Id$
+ *
+ * Copyright (c) 2004
  *      Daniel O'Connor <darius@dons.net.au>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without