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annotate 1wire-delay.h @ 14:a9d493261c6c

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- Add $Id$ - Rearrange slightly.
author darius
date Sat, 17 Sep 2005 18:02:28 +0930
parents eb1faf51968e
children 8dc98a293e43
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1 /*
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2 * Delay routines for the 1 wire bus
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3 * Search routine is copied from the Dallas owpd library with mods.
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4 *
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5 * $Id$
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6 *
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7 * Copyright (c) 2004
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8 * Daniel O'Connor <darius@dons.net.au>. All rights reserved.
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9 *
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions
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12 * are met:
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13 * 1. Redistributions of source code must retain the above copyright
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14 * notice, this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright
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16 * notice, this list of conditions and the following disclaimer in the
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17 * documentation and/or other materials provided with the distribution.
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18 *
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19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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29 * SUCH DAMAGE.
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30 */
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31
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32 /*
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33 * Note that all these routines are clock speed sensitive!
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34 * (4Mhz AT908515)
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35 */
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36
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37 #if (XTAL_CPU == 4000000)
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38 /* 6 usec */
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39 #define DELAY_A asm volatile( \
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40 "ldi r21, 6\n\t" \
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41 "L_%=: nop\n\t" \
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42 "dec r21\n\t" \
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43 "brne L_%=\n\t" \
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44 ::: "r21")
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45
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46 /* 64 usec */
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47 #define DELAY_B asm volatile( \
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48 "ldi r21, 32\n\t" \
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49 "L_%=: nop\n\t" \
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50 "nop\n\t" \
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51 "nop\n\t" \
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52 "nop\n\t" \
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53 "nop\n\t" \
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54 "dec r21\n\t" \
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55 "brne L_%=\n\t" \
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56 ::: "r21")
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57
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58 /* 60 usec */
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59 #define DELAY_C asm volatile( \
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60 "ldi r21, 30\n\t" \
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61 "L_%=: nop\n\t" \
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62 "nop\n\t" \
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63 "nop\n\t" \
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64 "nop\n\t" \
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65 "nop\n\t" \
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66 "dec r21\n\t" \
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67 "brne L_%=\n\t" \
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68 ::: "r21")
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69
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70 /* 10 usec */
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71 #define DELAY_D asm volatile( \
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72 "ldi r21, 9\n\t" \
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73 "L_%=: nop\n\t" \
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74 "dec r21\n\t" \
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75 "brne L_%=\n\t" \
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76 ::: "r21")
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77
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78 /* 9 usec */
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79 #define DELAY_E asm volatile( \
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80 "ldi r21, 8\n\t" \
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81 "L_%=: nop\n\t" \
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82 "dec r21\n\t" \
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83 "brne L_%=\n\t" \
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84 ::: "r21")
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85
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86 /* 55 usec */
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87 #define DELAY_F asm volatile( \
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88 "ldi r21, 27\n\t" \
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89 "L_%=: nop\n\t" \
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90 "nop\n\t" \
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91 "nop\n\t" \
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92 "nop\n\t" \
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93 "nop\n\t" \
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94 "nop\n\t" \
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95 "nop\n\t" \
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96 "nop\n\t" \
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97 "nop\n\t" \
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98 "nop\n\t" \
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99 "nop\n\t" \
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100 "nop\n\t" \
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101 "nop\n\t" \
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102 "dec r21\n\t" \
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103 "brne L_%=\n\t" \
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104 ::: "r21")
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105
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106 /* 0 usec */
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107 #define DELAY_G
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108
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109 /* 480 usec */
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110 #define DELAY_H asm volatile( \
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111 "ldi r21, 120\n\t" \
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112 "L_%=: nop\n\t" \
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113 "nop\n\t" \
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114 "nop\n\t" \
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115 "nop\n\t" \
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116 "nop\n\t" \
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117 "nop\n\t" \
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118 "nop\n\t" \
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119 "nop\n\t" \
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120 "nop\n\t" \
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121 "nop\n\t" \
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122 "nop\n\t" \
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123 "nop\n\t" \
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124 "nop\n\t" \
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125 "dec r21\n\t" \
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126 "brne L_%=\n\t" \
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127 ::: "r21")
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128
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129 /* 70 usec */
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130 #define DELAY_I asm volatile( \
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131 "ldi r21, 35\n\t" \
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132 "L_%=: nop\n\t" \
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133 "nop\n\t" \
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134 "nop\n\t" \
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135 "nop\n\t" \
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136 "nop\n\t" \
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137 "dec r21\n\t" \
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138 "brne L_%=\n\t" \
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139 ::: "r21")
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140 #else
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141 #error No 1 wire delay routines for selected clock speed
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142 #endif
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143