/*
 * Register abstraction for console code
 *
 * Copyright (c) 2008-2009
 *      Daniel O'Connor <darius@dons.net.au>.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/* Decide what registers and ISRs to use */
#ifdef UBRR0L
/* Dual UART devices (eg ATMega324p) */
#define _SETBAUD(x) do { \
	UBRR0L = (UART_BAUD_SELECT(x, F_CPU) & 0xff);		\
	UBRR0H = (UART_BAUD_SELECT(x, F_CPU) << 8) & 0xff;	\
    } while(0)

#define _INITREG() do {					\
	UCSR0A = 0;					\
	UCSR0B = _BV(RXEN0) | _BV(TXEN0) | _BV(RXCIE0);	\
	UCSR0C = _BV(UCSZ01) | _BV(UCSZ00);		\
    } while(0)
#define _UCSRA UCSR0A
#define _UDRE UDRE0
#define _RXC RXC0
#define _RXVECT USART0_RX_vect
#define _TXVECT USART0_TX_vect
#define _UDR UDR0
#else
#define _SETBAUD(x) do { \
	UBRRH = UART_BAUD_SELECT(x, F_CPU) >> 8;	\
	UBRRH = UART_BAUD_SELECT(x, F_CPU)  & 0xff;	\
    } while(0)
#define _INITREG() do {					\
	UCSRA = 0;					\
	UCSRB = _BV(RXEN) | _BV(TXEN) | _BV(RXCIE);	\
	UCSRC = _BV(UCSZ1) | _BV(UCSZ0);		\
    } while(0)
#define _UCSRA UCSRA
#define _UDRE UDRE
#define _RXC RXC
#define _UDR UDR

/* Handle vector name inconsistencies */
#ifdef USART_RXC_vect
#define _RXVECT USART_RXC_vect
#define _TXVECT USART_TXC_vect
#else
#define _RXVECT USART_RX_vect
#define _TXVECT USART_TX_vect
#endif
#endif