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comparison cons-reg.h @ 4:095216e8453d

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Hide register name abstraction in a separate file.
author darius@Inchoate
date Thu, 12 Mar 2009 16:30:47 +1030
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children f0b4314b91ec
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3:15d89caaf516 4:095216e8453d
1 /*
2 * Register abstraction for console code
3 *
4 * Copyright (c) 2008-2009
5 * Daniel O'Connor <darius@dons.net.au>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /* Decide what registers and ISRs to use */
30
31 #ifdef UBRR0
32 /* Dual UART devices (eg ATMega324p) */
33 #define _SETBAUD(x) do { \
34 UBRR0 = UART_BAUD_SELECT(x, F_CPU); \
35 } while(0)
36 #define _INITREG() do { \
37 UCSR0A = 0; \
38 UCSR0B = _BV(RXEN0) | _BV(TXEN0) | _BV(RXCIE0); \
39 UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); \
40 } while(0)
41 #define _UCSRA UCSR0A
42 #define _UDRE UDRE0
43 #define _RXC RXC0
44 #define _RXVECT USART0_RX_vect
45 #define _TXVECT USART0_TX_vect
46 #define _UDR UDR0
47 #else
48 #define _SETBAUD(x) do { \
49 UBRRH = UART_BAUD_SELECT(x, F_CPU) >> 8; \
50 UBRRH = UART_BAUD_SELECT(x, F_CPU) & 0xff; \
51 } while(0)
52 #define _INITREG() do { \
53 UCSRA = 0; \
54 UCSRB = _BV(RXEN) | _BV(TXEN) | _BV(RXCIE); \
55 UCSRC = _BV(UCSZ1) | _BV(UCSZ0); \
56 } while(0)
57 #define _UCSRA UCSRA
58 #define _UDRE UDRE
59 #define _RXC RXC
60 #define _UDR UDR
61
62 /* Handle vector name inconsistencies */
63 #ifdef USART_RXC_vect
64 #define _RXVECT USART_RXC_vect
65 #define _TXVECT USART_TXC_vect
66 #else
67 #define _RXVECT USART_RX_vect
68 #define _TXVECT USART_TX_vect
69 #endif
70 #endif
71