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annotate cons-reg.h @ 13:6f8f7b87d2f1

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- Rename 1wire config example to note it's for AVR. - Add STM32 config. - Rework a little to remove AVR depedencies. - Re-do OWProgROM in the no VPP case so it doesn't generate warnings.
author Daniel O'Connor <darius@dons.net.au>
date Tue, 07 Feb 2012 13:53:21 +1030
parents f0b4314b91ec
children
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1 /*
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2 * Register abstraction for console code
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3 *
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4 * Copyright (c) 2008-2009
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5 * Daniel O'Connor <darius@dons.net.au>. All rights reserved.
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6 *
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7 * Redistribution and use in source and binary forms, with or without
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8 * modification, are permitted provided that the following conditions
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9 * are met:
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10 * 1. Redistributions of source code must retain the above copyright
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11 * notice, this list of conditions and the following disclaimer.
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12 * 2. Redistributions in binary form must reproduce the above copyright
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13 * notice, this list of conditions and the following disclaimer in the
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14 * documentation and/or other materials provided with the distribution.
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15 *
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16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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26 * SUCH DAMAGE.
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27 */
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28
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29 /* Decide what registers and ISRs to use */
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30 #ifdef UBRR0L
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31 /* Dual UART devices (eg ATMega324p) */
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32 #define _SETBAUD(x) do { \
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33 UBRR0L = (UART_BAUD_SELECT(x, F_CPU) & 0xff); \
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34 UBRR0H = (UART_BAUD_SELECT(x, F_CPU) << 8) & 0xff; \
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35 } while(0)
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36
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37 #define _INITREG() do { \
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38 UCSR0A = 0; \
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39 UCSR0B = _BV(RXEN0) | _BV(TXEN0) | _BV(RXCIE0); \
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40 UCSR0C = _BV(UCSZ01) | _BV(UCSZ00); \
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41 } while(0)
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42 #define _UCSRA UCSR0A
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43 #define _UDRE UDRE0
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44 #define _RXC RXC0
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45 #define _RXVECT USART0_RX_vect
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46 #define _TXVECT USART0_TX_vect
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47 #define _UDR UDR0
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48 #else
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49 #define _SETBAUD(x) do { \
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50 UBRRH = UART_BAUD_SELECT(x, F_CPU) >> 8; \
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51 UBRRH = UART_BAUD_SELECT(x, F_CPU) & 0xff; \
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52 } while(0)
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53 #define _INITREG() do { \
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54 UCSRA = 0; \
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55 UCSRB = _BV(RXEN) | _BV(TXEN) | _BV(RXCIE); \
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56 UCSRC = _BV(UCSZ1) | _BV(UCSZ0); \
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57 } while(0)
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58 #define _UCSRA UCSRA
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59 #define _UDRE UDRE
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60 #define _RXC RXC
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61 #define _UDR UDR
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62
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63 /* Handle vector name inconsistencies */
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64 #ifdef USART_RXC_vect
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65 #define _RXVECT USART_RXC_vect
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66 #define _TXVECT USART_TXC_vect
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67 #else
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68 #define _RXVECT USART_RX_vect
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69 #define _TXVECT USART_TX_vect
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70 #endif
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71 #endif
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72